A semiconductor device having a high cutoff resistance capable of suppressing local current/electric field concentration and current concentration at a chip termination portion due to an electric field variation between IGBT cells due to a shape variation and impurity variation during manufacturing. The semiconductor device is characterized by including an emitter electrode formed on a front surface of a semiconductor substrate via an interlayer insulating film, a collector electrode formed on a back surface of the semiconductor substrate, a first semiconductor layer of a first conductivity type in contact with the collector electrode, a second semiconductor layer of a second conductivity type, a central area cell, and an outer peripheral area cell located outside the central area cell.

A semiconductor device includes a first electrode, a first conductive part, a semiconductor part, a second conductive part, a gate electrode and an insulating part. The first conductive part includes at least one of a metal, a metal oxide, or a metal nitride. The at least one of the metal, the metal oxide, or the metal nitride includes at least one selected from the group consisting of Ti, Ta, W, Cr, and Ru. The semiconductor part includes a first semiconductor region and a second semiconductor region. The first conductive part has a Schottky contact with the first semiconductor region. The second conductive part has a Schottky contact with the second semiconductor region. The second conductive part includes at least one selected from the group consisting of Pt, Ni, Ir, Pd, Au, and Co.

A semiconductor device includes a drain, a substrate, an epitaxial layer, and a semiconductor layer. The semiconductor layer includes a source region located on a side the semiconductor layer away from the epitaxial layer. A trench extending to the epitaxial layer is disposed on a side of the source region is away from the epitaxial layer. A gate, an electrode plate, a first shield gate, and a second shield gate are disposed in the trench. The electrode plate is located between the first shield gate and the second shield gate. The trench is further filled with an oxidized layer structure. The first shield gate and the second shield gate are separately spaced from the electrode plate to form electrode plate capacitance. One of the source region, the drain, and the gate is electrically connected to the electrode plate a first electrode, and a second one of the source region, the drain, and the gate is electrically connected to the shield gate structure.

A semiconductor device includes a semiconductor part, first to third electrodes, and a control electrode. The first electrode is provided on a back surface of the semiconductor part. The second electrode is provided at a front surface side of the semiconductor part. The third electrode and the control electrode are provided inside a trench of the semiconductor part. The control electrode includes first and second control portions. The semiconductor device further includes first to third insulating films. The first insulating film is between the control electrode and the semiconductor part. The second insulating film covers the first and second control portions. The third insulating film is between the second electrode and the second insulating film. The third insulating film includes a portion extending between the first and second control portions. The third electrode is between the first electrode and the extension portion of the third insulating film.

A semiconductor device includes: a semiconductor substrate; an epitaxial layer disposed on the substrate; a plurality of trenches formed in the epitaxial layer; a shield insulating layer formed inside the plurality of trenches; a shield electrode surrounded by the shield insulating layer and disposed inside the plurality of trenches; an inter-electrode insulating layer formed on top of the shield insulating layer and the shield electrode; a gate insulating layer disposed on the inter-electrode insulating layer; a gate electrode disposed on the gate insulating layer; a body region formed on an upper portion of the epitaxial layer located between the plurality of trenches; a source region formed on the body region; an inter-layer insulating layer formed on the gate electrode and the source region; and a body contact region in contact with the source region and the body region.

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming same. The structure comprises a semiconductor substrate including a trench, a source and a drain in the semiconductor substrate, a dielectric layer inside the trench, and a gate in the dielectric layer. The trench has a first sidewall and a second sidewall, the source is adjacent to the first sidewall of the trench, the drain is adjacent to the second sidewall of the trench, and the gate is laterally between the first sidewall of the trench and the second sidewall of the trench. The structure further comprises an air gap in the dielectric layer. The air gap is below the gate, and the air gap is laterally between the first sidewall of the trench and the second sidewall of the trench.

A semiconductor device includes: a semiconductor substrate; a drift zone of a first conductivity type in the semiconductor substrate; an array of interconnected gate trenches extending from a first surface of the semiconductor substrate into the drift zone; a plurality of semiconductor mesas delimited by the array of interconnected gate trenches; a plurality of needle-shaped field plate trenches extending from the first surface into the plurality of semiconductor mesas; in the plurality of semiconductor mesas, a source region of the first conductivity type and a body region of a second conductivity type separating the source region from the drift zone; and a current spreading region of the first conductivity type at the bottom of the gate trenches and having a higher average doping concentration than the drift zone. Methods of producing the semiconductor device are also described.

A field plate electrode FP is formed inside the trench TR via an insulating film IF1. The insulating film IF1 is retracted so that the position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP. An embedded insulating film EF1 is formed to cover the field plate electrode FP and the insulating film IF1. The embedded insulating film EF1 is retracted so that the position of the upper surface of the embedded insulating film EF1 is lower than the position of the upper surface of the field plate electrode FP. A gate insulating film GI is formed inside the trench TR, and an insulating film IF2 is formed to cover the field plate electrode FP. A gate electrode is formed on the field plate electrode FP via the insulating film IF2.

A semiconductor device includes a semiconductor layer; a trench formed in the semiconductor layer and including a side wall, an insulation layer formed on the semiconductor layer; and a gate electrode arranged in the trench. The insulation layer includes a gate insulation portion located between the semiconductor layer and the gate electrode, and covering the side wall of the trench. The gate electrode includes a first conductive portion contacting the gate insulation portion, and a second conductive portion including a side surface contacting the first conductive portion. The first conductive portion is formed from polysilicon, and the second conductive portion is formed from metal.

A transistor device and a method for manufacturing a transistor device are disclosed. The transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node; and a field electrode connected to a source node. The gate electrode is dielectrically insulated from the body region by a gate dielectric, and is arranged in a first trench extending from a first surface into the semiconductor body. The field electrode is dielectrically insulated from the drift region by a high-k dielectric, and is arranged in a second trench. The second trench extends from the first surface into the semiconductor body and is spaced apart from the first trench, and the field electrode extends at least as deep as the first trench into the semiconductor body.