Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

A method of forming a graphite-based structure on a substrate comprises patterning the substrate thereby forming a plurality of elements on the substrate. Each respective element in the plurality of elements is separated from an adjacent element on the substrate by a corresponding trench in a plurality of trenches on the substrate and each respective element in the plurality of elements has a corresponding top surface. The method further comprises segmentedly depositing a graphene initiating layer onto the top surface of each respective element in the plurality of elements; and generating graphene using the graphene initiating layer thereby forming the graphite-based structure.

A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer.

An oxide semiconductor film contains In, M (M is Al, Ga, Y, or Sn), and Zn and includes a region with a film density higher than or equal to 6.3 g/cm.sup.3 and lower than 6.5 g/cm.sup.3. Alternatively, the oxide semiconductor film contains In, M (M is Al, Ga, Y, or Sn), and Zn and includes a region with etching at an etching rate higher than or equal to 10 nm/min and lower than or equal to 45 nm/min when a phosphoric acid aqueous solution obtained by diluting 85 vol % phosphoric acid with water 100 times is used for etching.

The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.

A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region.

A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Disclosed are a semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor substrate; forming a first wordline trench structure; forming a first sacrificial layer at the bottom of the first wordline trench structure; filling the first wordline trench structure located in active regions by epitaxial growth; forming a first insulation layer covering the top of the semiconductor substrate and the first wordline trench structure; forming a second wordline trench structure and a fin-type structure in the active regions, a depth of the second wordline trench structure being less than that of the first wordline trench structure, and a projection of the second wordline trench structure in a vertical direction completely overlapping with a projection of the first sacrificial layer in the vertical direction; removing the first sacrificial layer; and filling the first wordline trench structure, the second wordline trench structure and the wordline tunnel.

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.