Provided is a semiconductor device comprising a diode portion that is arranged side by side with a transistor portion, wherein the transistor portion includes: a first contact portion in which a first mesa portion among a plurality of mesa portions and a metal electrode are in contact with each other; and a second contact portion in which a second mesa portion among the plurality of mesa portions, which is arranged further apart from the diode portion than the first mesa portion, and the metal electrode is in contact with each other, and a lower end of the first contact portion is arranged above a lower end of the second contact portion.

Provided is a semiconductor device including an MOS gate structure, comprising: an underlying layer provided on a front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer dielectric film provided above the underlying layer; a contact hole provided in the interlayer dielectric film and reaching the underlying layer from an upper surface of the interlayer dielectric film; a first alloy layer provided on a bottom portion of the contact hole; and a second alloy layer provided on a side wall of the contact hole. Provided is a manufacturing method of a semiconductor device including: depositing an initial polycrystalline film and a first initial metal film on an inner wall of the contact hole; and forming a first alloy layer on a bottom portion of the contact hole and forming a second alloy layer on a side wall of the contact hole, by heating the semiconductor substrate.

A semiconductor device including a gate electrode layer embedded in a gate trench, a contact trench including a first intersection region intersecting the gate trench, and an emitter contact electrode layer embedded in the contact trench, in which gate electrode recess portions are formed in the first intersection region in the gate trench and a peripheral portion of the first intersection region, a gate covering insulating layer is embedded in the gate electrode recess portion, and the emitter region is formed deeper than an upper surface of the gate electrode layer in the periphery of the first intersection region.

A semiconductor device including a gate electrode embedded in a gate trench, a surface insulating layer formed on a first principal surface and having a contact hole, a covering insulating layer covering the gate electrode in the gate trench and insulating the gate electrode and the contact electrode from each other, and an embedded body embedded in a region on the covering insulating layer in the gate trench and having an etching selectivity to the surface insulating layer.

A semiconductor device including: an interlayer dielectric film provided between an upper surface of a semiconductor substrate and an upper surface electrode and having a first contact hole connecting the semiconductor substrate and the upper surface electrode; a protection film provided on an upper surface of the upper surface electrode; and a plating layer provided on a region, which is not covered with the protection film, of the upper surface of the upper surface electrode, wherein the semiconductor substrate has a first end side in a top view, the first contact hole includes a first outer hole end portion closest to the first end side, and the plating layer is formed on a portion, which overlaps with the first outer hole end portion, of the upper surface electrode.

A semiconductor device including a transistor portion and a diode portion is provided, the semiconductor device including: a plurality of trench portions provided at a front surface of a semiconductor substrate; a drift region of a first conductivity type; a base region of a second conductivity type; an emitter region of the first conductivity type having a higher doping concentration than the drift region; a first contact region of the second conductivity type having a higher doping concentration than the base region; an anode region of the second conductivity type; and a second contact region of the second conductivity type having a higher doping concentration than the anode region, wherein an amount per unit volume of dopants of the second conductivity type in the mesa portion of the diode portion is greater than or equal to that in the mesa portion of the transistor portion.

Provided is a semiconductor apparatus comprising: a semiconductor substrate; an element electrode provided above the semiconductor substrate; an element electrode pad electrically connected to the element electrode; and a wire configured to connect to the element electrode pad at a plurality of connection points, wherein the semiconductor substrate includes an emitter region of a first conductivity type arrayed in an array direction, the emitter region facing the element electrode on an upper surface of the semiconductor substrate, wherein a density of the emitter region below a connection point of any of the wires is different from a density of the emitter region below a connection point of any other of the wires.

An object is to provide a technology that can suppress a failure of embedding a metal layer in recesses of an alloy layer to improve the adhesive strength between the metal layer and the alloy layer. A semiconductor device includes: a semiconductor substrate; an alloy layer on the semiconductor substrate, the alloy layer containing a semiconductor material of the semiconductor substrate as a main component; and a metal layer on the alloy layer. A plurality of recesses is discretely formed in a surface of the alloy layer which is closer to the metal layer, and 90% or more of the recesses have a bowl shape which monotonously decreases as an opening width of each of the recesses proceeds to a depth portion of the recess.

A semiconductor module includes a laminated substrate including an insulating board and a plurality of circuit boards that are arranged on an upper face of the insulating board, the plurality of circuit boards including first and second circuit boards, a semiconductor element disposed on the first circuit board and including, on an upper face of the semiconductor element, a main electrode, a gate pad, and a gate runner electrically connected to the gate pad, and a first wiring member electrically connecting the main electrode to the second circuit board. The gate runner extends so as to divide the main electrode into a plurality of electrodes including a first main electrode at a first side and a second main electrode at a second side, and the first wiring member is arranged to cross over the gate runner.

A semiconductor device includes: a semiconductor substrate; a trench gate portion on the semiconductor substrate; a surface electrode covering an upper side of the semiconductor substrate; and an interlayer insulating film insulating the trench gate portion from the surface electrode. The semiconductor substrate includes: a drift region; a body region above the drift region; a barrier region below at least a part of the body region; and a pillar region extending from the surface of the semiconductor substrate to the barrier region and in Schottky contact with the surface electrode. The interlayer insulating film has an acute angle between a top surface and a side surface thereof.