A semiconductor device includes a first electrode, a first conductive part, a semiconductor part, a second conductive part, a gate electrode and an insulating part. The first conductive part includes at least one of a metal, a metal oxide, or a metal nitride. The at least one of the metal, the metal oxide, or the metal nitride includes at least one selected from the group consisting of Ti, Ta, W, Cr, and Ru. The semiconductor part includes a first semiconductor region and a second semiconductor region. The first conductive part has a Schottky contact with the first semiconductor region. The second conductive part has a Schottky contact with the second semiconductor region. The second conductive part includes at least one selected from the group consisting of Pt, Ni, Ir, Pd, Au, and Co.

An SGT MOSFET comprising a substrate, an epitaxial layer, a masking dielectric layer, an interlayer dielectric layer, a source lead-out contact hole, and a source conductive layer and a method for manufacturing the SGT MOSFET are provided. The epitaxial layer is on an upper surface of the substrate and comprises a cellular trench structure, a terminal lead-out structure, a source lead-out structure, a body region, and a source region. The source lead-out structure comprises a source lead-out conductive layer. The masking dielectric layer and the interlayer dielectric layer are sequentially stacked above the epitaxial layer. The source lead-out contact hole penetrates the interlayer dielectric layer and the masking dielectric layer and extends into the source lead-out conductive layer, The source conductive layer fills the source lead-out contact hole. The masking dielectric layer is formed between the interlayer dielectric layer and the epitaxial layer and masks the third dielectric layer.

A silicon carbide semiconductor device, comprising: a silicon carbide epitaxial layer, wherein the silicon carbide epitaxial layer comprises a first surface and a second surface that are opposite to each other, the first surface comprises a gate region and a source region located on two sides of the gate region; a first trench, opened at the first surface in the gate region; a first voltage-resistant shielding structure in the silicon carbide epitaxial layer and surrounding a lower part of the first trench; a gate structure in the first trench; a gate metal on a surface of the gate structure; a second voltage-resistant shielding structure, embedded under the first surface in the source portion; a source metal on the first surface in the source region; and a doped well, embedded under the first surface and located between the first trench and the second voltage-resistant shielding structure.

An SGT MOSFET comprising a substrate, an epitaxial layer, a masking dielectric layer, an interlayer dielectric layer, a source lead-out contact hole, and a source conductive layer and a method for manufacturing the SGT MOSFET are provided. The epitaxial layer is on an upper surface of the substrate and comprises a cellular trench structure, a terminal lead-out structure, a source lead-out structure, a body region, and a source region. The source lead-out structure comprises a source lead-out conductive layer. The masking dielectric layer and the interlayer dielectric layer are sequentially stacked above the epitaxial layer. The source lead-out contact hole penetrates the interlayer dielectric layer and the masking dielectric layer and extends into the source lead-out conductive layer, The source conductive layer fills the source lead-out contact hole. The masking dielectric layer is formed between the interlayer dielectric layer and the epitaxial layer and masks the third dielectric layer.

A semiconductor device includes a semiconductor base body, a plurality of trenches, a gate insulation film, a gate electrode, an interlayer insulation film, and a surface electrode. The semiconductor base body has a protruding region of a second conductive type that is formed so as to protrude from a bottom portion of a second-conductive-type semiconductor region and is spaced apart from a trench, a peak position of dopant concentration of the protruding region is deeper than a bottom portion of the second-conductive-type semiconductor region, a total amount of dopants in a depth-direction cross section of the protruding region is equal to or smaller than a total amount of dopants in a depth-direction cross section of the second-conductive-type region.

A semiconductor device according to an embodiment includes: a first electrode; a second electrode opposing the first electrode in a first direction; a semiconductor part provided between the first electrode and the second electrode; a metal silicide layer provided between the second electrode and the semiconductor part; and a metal layer provided between the metal silicide layer and the second electrode. The metal silicide layer includes a recess recessed toward the semiconductor part. The metal layer contacts a bottom surface and a side surface of the recess.

A vertical semiconductor device with a continuous gate length and a method of manufacturing the same, and an electronic apparatus including the same. The semiconductor device includes: a semiconductor base on a substrate; first and second vertical channel portions on the semiconductor base, where the first and second vertical channel portions are vertical relative to the substrate, protrude from the semiconductor base, are spaced apart from in a first direction and self-aligned with each other, and the semiconductor base extends continuously between the first and second vertical channel portions; a first source/drain portion and a second source/drain portion on the first vertical channel portion and the second vertical channel portion, respectively; and a gate stack at least partially on the first vertical channel portion, the semiconductor base, and the second vertical channel portion to define a continuous channel between the first source/drain portion and the second source/drain portion.

A device having reduced Rds(on) is described. The device comprises a unit cell. The unit cell comprises: a first region, a second region, a third region, and a fourth region. The fourth region is residing on the first region, the second region, and the third region. The second region connects the first region and the third region. The first region, the second region and the third region are of same conductivity type (e.g., second conductivity type). In an embodiment, the fourth region comprises a fifth region and a sixth region. The fourth region, the fifth region, and the sixth region are of same conductivity type (e.g., first conductivity type). The fourth region is on the first region. The fifth region is on the second region. The sixth region is on the third region. In an embodiment, the device achieves reduced Rds(on) by relaxing the JFET constraint.

A semiconductor device includes first to third electrodes, a semiconductor part, a control electrode and an insulating body. The second electrode is opposite to the first electrode. The semiconductor part is provided between the first electrode and the second electrode. The semiconductor part includes first and second trenches next to each other in a front side facing the second electrode. The second trench has a first width in a first direction directed from the first trench toward the second trench. The third electrode and the control electrode are provided inside the first trench. Another third electrode and the insulating body is provided inside the second trench. The insulating body is positioned in the second trench between said another third electrode and the second electrode. The insulating body has a second width in the first direction. The second width is equal to the first width of the second trench.

A semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer and having a side wall and a bottom wall, a field plate electrode formed in the trench, a gate electrode formed in the trench, and an insulation layer that isolates the field plate electrode and the gate electrode from each other and covers the side wall and the bottom wall in the trench. The semiconductor layer includes a drift region and a body region formed on the drift region. An interface of the drift region and the body region lies between a lower end position of the gate electrode and a reference position that is located upward from the lower end position by the thickness of the gate electrode in the depth direction.