A semiconductor device includes a backside power delivery network (BSPDN). The semiconductor device includes a substrate, a first active pattern extending in a first direction, on a top surface of the substrate, a second active pattern extending in the first direction, and spaced apart from the first active pattern in a second direction intersecting the first direction, on the top surface of the substrate, a gate structure extending in the second direction, on the first active pattern and the second active pattern, a first source/drain pattern connected to the first active pattern, on a side surface of the gate structure, a second source/drain pattern connected to the second active pattern, on the side surface of the gate structure, back source/drain contacts penetrating the substrate, and a first power line connected to the back source/drain contacts on a bottom surface of the substrate.

A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structures having an n-type metal oxide semiconductor (n-MOS) region and/or a p-type MOS (p-MOS) region, the cavity shaping process comprising forming an n-MOS cavity in an exposed surface of the n-MOS region and/or a p-MOS cavity in an exposed surface of the p-MOS region, wherein the cavity shaping process is configured to increase the surface area of the exposed surface of the n-MOS region or the p-MOS region. In some embodiments, the method includes performing a first selective deposition process to form a p-MOS cavity contact, selectively in the p-MOS cavity.

An integrated circuit device includes a first semiconductor substrate having a frontside surface and a backside surface opposite to each other, an FEOL structure on the frontside surface of the first semiconductor substrate, a first BEOL structure on the FEOL structure, a second BEOL structure on the backside surface of the first semiconductor substrate, and a second semiconductor substrate apart from the first semiconductor substrate in a vertical direction with the FEOL structure and the first BEOL structure The second semiconductor substrate is locally bonded to the first BEOL structure. The second semiconductor substrate includes a main surface facing the first BEOL structure, and the main surface of the second semiconductor substrate defines a local trench region in which trenches are defined in a regular pattern and local bonding areas bonded to the first BEOL structure.

A chip includes one or more first channels extending in a first direction, a first epitaxial (epi) layer coupled to the one or more first channels, one or more second channels extending in the first direction, a second epi layer coupled to the one or more second channels, and a dielectric wall disposed between the first epi layer and the second epi layer.

A semiconductor device structure is described. The structure includes a fin structure formed on a substrate, a source/drain feature disposed adjacent the fin structure and over the substrate, wherein a top surface of the source/drain feature and a front side of the substrate are substantially co-planar, an isolation trench extending from the front side of the substrate towards a backside of the substrate, and a backside via contact extending from the backside of the substrate towards and in contact with the source/drain feature, wherein the backside via contact and the isolation trench are parallelly arranged and separated from each other by a constant gap along boundaries of the backside via contact and the isolation trench.

An example semiconductor device includes a substrate, a channel layer disposed on the substrate, a gate structure surrounding the channel layer, source/drain patterns connected with both sides of the channel layer, a lower wiring structure disposed below the substrate, and an insulating pattern extending through the substrate and disposed between the source/drain patterns below the gate structure. The insulating pattern includes a sub-insulating pattern disposed below the gate structure and a main insulating pattern disposed between the sub-insulating pattern and the lower wiring structure. The sub-insulating pattern and the main insulating pattern include different insulating materials.

An integrated circuit device includes a first gate line and a second gate line adjacent to each other in a first horizontal direction and extending in a second horizontal direction that is perpendicular to the first horizontal direction, a source/drain region between the first gate line and the second gate line, a backside via contact connected to the source/drain region, and a first backside bulk insulating film and a second backside bulk insulating film, where, in the first horizontal direction, the backside via contact is between the first backside bulk insulating film and the second backside bulk insulating film, where each of the first backside bulk insulating film and the second backside bulk insulating film includes a vertical insulating portion below one gate line among the first gate line and the second gate line in a vertical direction and extending in the vertical direction.

A semiconductor device includes: a substrate including active patterns; a device isolation layer disposed between the active patterns; a stacked pattern disposed on the substrate; a power transmission network layer disposed on a first surface of the substrate; a first through via penetrating the stacked pattern; and a second through via disposed between the power transmission network layer and the first through via, wherein the second through via penetrates the active patterns and the device isolation layer.

Provided is a semiconductor device including a substrate, a lower power line disposed under the substrate, a source/drain pattern on the substrate, a channel pattern, on side surfaces of the source/drain pattern, including a plurality of semiconductor patterns stacked on each other, a gate electrode between the plurality of semiconductor patterns, a backside active contact penetrating the substrate to electrically connect the lower power line and the source/drain pattern, and a backside isolation structure penetrating the substrate and the backside active contact, and disposed under the gate electrode. An uppermost surface of the backside active contact is located at a higher level than an uppermost surface of the backside isolation structure.

Provided is a semiconductor device including: a substrate; an active pattern on an upper side of the substrate; a gate structure on and intersecting the active pattern; a source/drain pattern on a side face of the gate structure and connected to the active pattern; an etch stop layer extending along an upper side of the substrate and an outer face of the source/drain pattern; a back side source/drain contact in the substrate, the back side source/drain contact being connected to the source/drain pattern; and a back side wiring structure on a lower side of the substrate and connected to the back side source/drain contact, wherein the back side source/drain contact extends along a part of a side face of the source/drain pattern, and wherein a part of the back side source/drain contact farthest from the lower side of the substrate is in contact with the etch stop layer.