Transistor devices having metal structures with rounded corners are provided. In one example, The transistor device includes a Group III-nitride semiconductor structure. The transistor device includes a gate contact and/or a field plate on the Group III-nitride semiconductor structure. One or more of the gate contact or the field plate includes at least one rounded corner.

An integrated semiconductor device includes a silicon body that includes <111> single crystal silicon, a semiconductor device that is disposed within the silicon body, a III-nitride body disposed on the silicon body, and a III-nitride device that is disposed within the III-nitride body, wherein the semiconductor device is operatively coupled to the III-nitride device.

A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

A nitride semiconductor device includes an electron transit layer, an electron supply layer disposed on the electron transit layer to generate two-dimensional electron gas in the electron transit layer, a gate layer containing acceptor impurities and disposed on the electron supply layer, a gate electrode contacting the gate layer, a source electrode, and a drain electrode. The gate layer includes a trench that is recessed from an upper surface of the gate layer in a region contacting the gate electrode. The trench includes a trench open end, a trench bottom surface, and a curved surface continuous with the trench bottom surface and curved from the trench bottom surface toward the trench open end.

A power amplifier semiconductor device includes: a substrate; a semiconductor layer provided on the surface of the substrate and including a plurality of unit HEMTs; a connection layer provided on the semiconductor layer and including a source electrode, a drain electrode, and a gate electrode of each of the plurality of unit HEMTs; a terminal layer provided on the connection layer; a back electrode which is provided on the bottom surface of the substrate and whose potential is set to a source potential; and substrate vias that pass through the substrate and have a shield wiring layer on inner walls of the substrate vias. In plan view, either one of the drain aggregation portion or the gate aggregation portion is or both of the drain aggregation portion and the gate aggregation portion are each surrounded by the substrate vias.

A technique for making contact to the cap layers in multifinger III-Nitride transistors with cap layers is described. A contact structure is disposed at an end of the transistor device and connects to the cap layer of individual fingers of the transistor device using a cap contact bus. A transistor is also described that includes a contact structure that is used to move the cap layer contact away from the individual fingers. Transistors may be created using unit cells, wherein each unit cell includes a contact structure and cap contact bus.

A semiconductor device includes: a gate electrode including a junction portion forming a Schottky junction with a barrier layer; a projecting portion including first and second gate field plates and projecting from the junction portion; and an insulating layer including first and second sidewalls. An angle formed between a highest position of a bottom surface of the first gate field plate and a main surface of a substrate, viewed from the first position, is a second elevation angle. An angle formed between an end on the drain electrode side of a lowest portion of a bottom surface of the second gate field plate and the main surface, viewed from the first position, is a third elevation angle. The second elevation angle is larger than the third elevation angle. The bottom surface of the second gate field plate includes an inclined surface where a distance from the barrier layer monotonically increases.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

A semiconductor device includes a drain electrode, a first source electrode, a second source electrode, a first gate electrode, and a second gate electrode. The first gate electrode is arranged between the first source electrode and the drain electrode. The first gate electrode extends along a first direction. The second gate electrode is arranged between the second source electrode and the drain electrode. The second gate electrode extends along the first direction. The first gate electrode is arranged above a first imaginary line substantially perpendicular to the first direction in a top view of the semiconductor device and the second gate electrode is arranged below a second imaginary line substantially perpendicular to the first direction in the top view of the semiconductor device.

A nitride semiconductor device includes an electron transit layer, an electron supply layer, a gate layer containing acceptor impurities, a gate electrode, a passivation layer, a source electrode, a drain electrode, and a field plate electrode. The field plate electrode is located on the passivation layer between the gate layer and the drain electrode. The gate layer includes a ridge where the gate electrode is located, a source-side extension extending from the ridge, and a drain-side extension extending from the ridge to a side opposite to the source-side extension. The passivation layer includes a field plate non-overlapping region that does not overlap the field plate electrode and is located immediately above the drain-side extension.