Present invention relates to a semiconductor device including a buried gate structure. A semiconductor device comprises a substrate; a first fluorine-containing layer over the substrate; a trench formed in the first fluorine-containing layer and extended into the substrate; a gate dielectric layer formed over the trench; a gate electrode formed over the gate dielectric layer and filling a portion of the trench; a second fluorine-containing layer formed over the gate electrode; and a fluorine-containing passivation layer between the gate dielectric layer and the gate electrode.

A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face and including a first trench, a second trench having a distance of 100 nm or less from the first trench, a first silicon carbide region of n-type, a second silicon carbide region of p-type between the first trench and the second trench, a third silicon carbide region of n-type between the second silicon carbide region and the first face, a fourth silicon carbide region between the first trench and the second silicon carbide region and containing oxygen, and a fifth silicon carbide region between the second trench and the second silicon carbide region and containing oxygen; a first gate electrode in the first trench; a second gate electrode in the second trench; a first gate insulating layer; a second gate insulating layer; a first electrode; and a second electrode.

In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

A field plate electrode FP is formed inside the trench TR via an insulating film IF1. The insulating film IF1 is retracted so that the position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP. An embedded insulating film EF1 is formed to cover the field plate electrode FP and the insulating film IF1. The embedded insulating film EF1 is retracted so that the position of the upper surface of the embedded insulating film EF1 is lower than the position of the upper surface of the field plate electrode FP. A gate insulating film GI is formed inside the trench TR, and an insulating film IF2 is formed to cover the field plate electrode FP. A gate electrode is formed on the field plate electrode FP via the insulating film IF2.

A semiconductor device includes a semiconductor layer including a first surface and a second surface opposite to the first surface; a source trench formed in the semiconductor layer and including a side wall that is continuous with the second surface; an insulation layer formed on the second surface of the semiconductor layer; an embedded electrode arranged in the source trench and insulated from the side wall of the source trench by the insulation layer; a source interconnection formed on the insulation layer; and a source contact plug electrically connecting the source interconnection to the semiconductor layer. The source contact plug contacts the embedded electrode, and the source contact plug contacts the semiconductor layer via a part of the side wall of the source trench.

A transistor device and a method for manufacturing a transistor device are disclosed. The transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node; and a field electrode connected to a source node. The gate electrode is dielectrically insulated from the body region by a gate dielectric, and is arranged in a first trench extending from a first surface into the semiconductor body. The field electrode is dielectrically insulated from the drift region by a high-k dielectric, and is arranged in a second trench. The second trench extends from the first surface into the semiconductor body and is spaced apart from the first trench, and the field electrode extends at least as deep as the first trench into the semiconductor body.

Contact over active gate (COAG) structures with a tapered gate or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers. A conductive structure is in direct contact with the conductive cap and sidewall spacers on one of the plurality of gate structures or with the conductive cap and sidewall spacers on one of the plurality of conductive trench contact structures.

A power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.