In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A data storage structure is arranged over the substrate and laterally between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the data storage structure. The first doped region is laterally between the isolation structure and the data storage structure. A remnant is arranged over and along a sidewall of the isolation structure. The remnant includes a first material having a vertically extending segment and a horizontally extending segment protruding outward from a sidewall of the vertically extending segment.

A semiconductor device comprising: a substrate including an active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode extending in a first direction on the channel pattern, wherein the gate electrode includes an inner gate electrode between first and second semiconductor patterns among the plurality of semiconductor patterns; and an inner gate spacer between the inner gate electrode and the source/drain pattern, wherein the inner gate spacer includes a center portion and an edge portion, the center portion has a first thickness in a second direction, the edge portion has a second thickness in the second direction, the first thickness is greater than the second thickness, the first and second semiconductor patterns are adjacent to each other in a third direction.

A semiconductor device includes a substrate, a first unit FET including first source, first drain, and first gate electrodes, a second unit FET including second source, second drain, and second gate electrodes, a first source wiring electrically contacting the first source electrode, a gate bus bar electrically connected to the first gate electrode, and interposing the first gate electrode between the gate bus bar and the second gate electrode, and a gate wiring provided above the first source electrode in non-contact with the first source electrode, and electrically connecting the gate bus bar and the second gate electrode, wherein a maximum width in a first direction of a region where the first source wiring contacts the first source electrode is times or more a maximum width in the first direction of a region where the first source wiring overlaps the first source electrode.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Embodiments of the invention are directed to a transistor device that includes a channel stack having stacked, spaced-apart, channel layers. A first source or drain (S/D) region is communicatively coupled to the channel stack. A tunnel extends through the channel stack, wherein the tunnel includes a central region and a first set of end regions. The first set of end regions is positioned closer to the first S/D region than the central region is to the first S/D region. A first type of work-function metal (WFM) is formed in the first set of end regions, the first WFM having a first work-function (WF). A second type of WFM is formed in the central region, the second type of WFM having a second WF, wherein the first WF is different than the second WF.

A semiconductor device includes a substrate; a channel region disposed in the substrate; and a diffusion region disposed in the substrate on a side of the channel region. The diffusion region comprises a LDD region and a heavily doped region within the LDD region. A gate electrode is disposed over the channel region. The gate electrode partially overlaps with the LDD region. A spacer is disposed on a sidewall of the gate electrode. A gate oxide layer is disposed between the gate electrode and the channel region, between the gate electrode and the LDD region, and between the spacer and the LDD region. A silicide layer is disposed on the heavily doped region and is spaced apart from the edge of the spacer.

The present disclosure relates to semiconductor devices and their fabrication methods. An example semiconductor device comprises a substrate including an active pattern, a channel pattern including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, an inner gate electrode between two neighboring semiconductor patterns, an inner gate dielectric layer, and an inner high-k dielectric layer between the inner gate electrode and the inner gate dielectric layer. The inner gate dielectric layer includes an upper dielectric layer, a lower dielectric layer, and an inner spacer. A first thickness of the inner spacer is greater than a second thickness of the upper or lower dielectric layer. The first thickness is greater than a third thickness of the inner high-k dielectric layer.

A vertical channel transistor includes a substrate having a bit line thereon, and a vertical channel layer including a first metal oxide, on the bit line. A lower insertion layer is provided, which extends between the bit line and a first end of the channel layer, and includes a second metal oxide having a greater bonding energy relative to the first metal oxide. A lower source/drain region is provided, which extends between the first end of the channel layer and the lower insertion layer, and includes a first metal dopant that is a reduced form of the first metal oxide. An upper source/drain region is provided, which is electrically connected to a second end of the channel layer, and includes the first metal dopant. An insulated gate line is provided on the channel layer.

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain portion adjacent to the gate electrode, and a semiconductor layer between the gate electrode and the source/drain portion.

Contact over active gate (COAG) structures with a tapered gate or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers. A conductive structure is in direct contact with the conductive cap and sidewall spacers on one of the plurality of gate structures or with the conductive cap and sidewall spacers on one of the plurality of conductive trench contact structures.