A semiconductor device having a high cutoff resistance capable of suppressing local current/electric field concentration and current concentration at a chip termination portion due to an electric field variation between IGBT cells due to a shape variation and impurity variation during manufacturing. The semiconductor device is characterized by including an emitter electrode formed on a front surface of a semiconductor substrate via an interlayer insulating film, a collector electrode formed on a back surface of the semiconductor substrate, a first semiconductor layer of a first conductivity type in contact with the collector electrode, a second semiconductor layer of a second conductivity type, a central area cell, and an outer peripheral area cell located outside the central area cell.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped active region over a substrate and comprising a number of channel layers interleaved by a number of sacrificial layers, removing a source/drain region of the fin-shaped active region to form a source/drain opening, forming a source/drain feature in the source/drain opening, selectively removing the number of sacrificial layers to form a number of gate openings, and forming a gate structure in the number of gate openings, where the gate structure includes a first portion formed in a first gate opening of the number of gate openings and a second portion formed in a second gate opening of the number of gate openings, a gate length of the first portion is different from a gate length of the second portion.

To provide a semiconductor device and an imaging apparatus capable of improving performance of a transistor. The semiconductor device includes a semiconductor substrate and a transistor provided on the semiconductor substrate. A gate electrode of the transistor includes a first part disposed at a position opposing the semiconductor substrate via a gate insulating film of the transistor and configured to form a channel on the semiconductor substrate and a second part positioned on top of the first part and configured to have a smaller contribution toward the formation of the channel than the first part. The first part includes a gate end which is positioned on a side of one region of a drain region and a source region of the transistor and in which an electric field concentrates with respect to the one region. The gate end is positioned above or below a surface of the one region via a stepped portion provided on a side of a first surface of the semiconductor substrate and is flush with a side surface of the second part.

A semiconductor device includes a semiconductor part, first to third electrodes, and a control electrode. The first electrode is provided on a back surface of the semiconductor part. The second electrode is provided at a front surface side of the semiconductor part. The third electrode and the control electrode are provided inside a trench of the semiconductor part. The control electrode includes first and second control portions. The semiconductor device further includes first to third insulating films. The first insulating film is between the control electrode and the semiconductor part. The second insulating film covers the first and second control portions. The third insulating film is between the second electrode and the second insulating film. The third insulating film includes a portion extending between the first and second control portions. The third electrode is between the first electrode and the extension portion of the third insulating film.

A semiconductor device includes a silicon substrate, a first layer, a second layer, a barrier metal, and a gate pad. The first layer is formed of an oxide film provided on an upper surface of the silicon substrate. The second layer is a layer at least selectively having a projecting and recessed part on an upper surface of the first layer, the projecting and recessed part having a projection and recess deeper than a projection and recess occurring when the layer is formed in a planar shape. The barrier metal is formed on an upper surface of the second layer according to a shape of the projecting and recessed part. The gate pad is in close contact with the silicon substrate via the barrier metal.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a substrate, a source region, a drain region and a gate structure. The source region is located in the substrate. The drain region is located in the substrate. The gate structure is disposed on the substrate and located between the source region and the drain region, and includes a first sub-gate structure and a second sub-gate structure. The first sub-gate structure is adjacent to the source region and includes a first sub-gate insulating layer. The second sub-gate structure is adjacent to the drain region and includes a second sub-gate insulating layer. The second sub-gate insulating layer and the first sub-gate insulating layer are separated from each other. The first sub-gate insulating layer has a first thickness, and the second sub-gate insulating layer has a second thickness greater than the first thickness.

The embodiments of the disclosure provide a FinFET. The FinFET includes a substrate, a first gate stack and a second gate stack. The substrate has a first fin and a second fin. The first gate stack is across the first fin and extends along a widthwise direction of the first fin. The second gate stack is across the second fin and extends along a widthwise direction of the second fin. A bottommost surface of the first gate stack is lower than a bottommost surface of the second gate stack, and a first gate height of the first gate stack directly on the first fin is substantially equal to a second gate height of the second gate stack directly on the second fin.

The present disclosure describes a structure including a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate and a method of forming the structure. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.

A method includes forming an active region on a substrate, forming a sacrificial gate stack engaging the active region, measuring a gate length of the sacrificial gate stack at a height lower than a top surface of the active region, selecting an etching recipe based on the measured gate length of the sacrificial gate stack, etching the sacrificial gate stack with the etching recipe to form a gate trench, and forming a metal gate stack in the gate trench.