A semiconductor device includes a substrate, a first dielectric layer, a channel layer and source/drain electrodes. The first dielectric layer is over the substrate. The channel layer is over the first dielectric layer. Source/drain electrodes are over the channel layer. The source/drain electrodes comprise a 2D semimetal material. The channel layer comprises a 2D semiconductor material interfacing the 2D semimetal material of the source/drain electrodes.

A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.

A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.

Disclosed is a manganese tin oxide-based transparent conducting oxide (TCO) with an optimized composition, which has low surface roughness, low sheet resistance and high transmittance even when deposited at room temperature, a multilayer transparent conductive film using the same and a method for fabricating the same. The manganese tin oxide-based transparent conducting oxide has a composition of Mn.sub.xSn.sub.1-xO (0<x0.055), and the multilayer transparent conductive film includes: a manganese tin oxide-based transparent conducting oxide having a composition of Mn.sub.xSn.sub.1-xO (0<x0.055); a metal thin film deposited on the manganese tin oxide-based transparent conducting oxide; and a manganese tin oxide-based transparent conducting oxide having a composition of Mn.sub.xSn.sub.1-xO (0<x0.055) deposited on the metal thin film.

The present disclosure relates to a single crystal metal film containing hydrogen atoms or hydrogen ions, which is oriented only in the (111) crystal plane on a substrate or without a substrate, and a method for preparing the same.

According to the present disclosure, a single crystal metal film containing hydrogen atoms or hydrogen ions, which is oriented only in the (111) crystal plane, can be formed in various shapes such as a foil, a plate, a block or a tube even without an expensive substrate only by heat-treating a metal precursor having crystallinity and preference for orientation in the crystal plane under a hydrogen atmosphere. Because electrical conductivity is improved due to the contained hydrogen atoms or hydrogen ions, the single crystal metal film can be used as a material for a display driver IC, a semiconductor device, a lithium secondary battery, a fuel cell, a solar cell or a gas sensor.

A semiconductor device is provided that is excellent in semiconductor properties and Schottky characteristics. A semiconductor device includes: a semiconductor layer containing a crystalline oxide semiconductor with a corundum structure as a major component; and a Schottky electrode on the semiconductor layer, wherein the Schottky electrode is formed by containing a metal of Groups 4-9 of the periodic table, thereby manufacturing a semiconductor device excellent in semiconductor properties and Schottky characteristics without impairing the semiconductor properties to use the semiconductor device thus obtained for a power device and the like.

Provided are a graphene pattern and a process of preparing the same. Graphene is patterned in a predetermined shape on a substrate to form the graphene pattern. The graphene pattern can be formed by forming a graphitizing catalyst pattern on a substrate, contacting a carbonaceous material with the graphitizing catalyst and heat-treating the resultant.

The transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer.

A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.

A transparent electrode including: a substrate; a first layer disposed on the substrate, the first layer including a graphene mesh structure, the graphene mesh structure including graphene and a plurality of holes; and a second layer disposed on the first layer, wherein the second layer includes a plurality of conductive nanowires.