A method of manufacturing a silicon carbide semiconductor device includes preparing a silicon carbide semiconductor substrate in which, on a front surface of a starting substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided, the first semiconductor layer having an impurity concentration lower than an impurity concentration of the starting substrate. Next, at the surface of the first semiconductor layer, a second semiconductor layer of a second conductivity type is formed. Next, at the surface of the second semiconductor layer, an ohmic electrode is formed. Next, at the surface of the ohmic electrode, a Ti film and a TiN film are sequentially deposited to form a barrier metal. Next, the barrier metal is subjected to a heat treatment to form an annealed barrier metal. The heat treatment is performed in a range of 550 degrees C. to 750 degrees C.

Thermal stability of a transistor is improved in different ways. An interfacial layer between a source/drain electrode and a semiconductor layer is formed from a material having a higher bond dissociation energy than indium oxide. Alternatively, the interfacial layer is formed from a metal-doped oxide semiconductor material. As another option, a metal layer or a metal oxide layer is formed between the source/drain electrode and the interfacial layer.

A semiconductor structure includes: a substrate; a gate structure located on the substrate, wherein the gate structure comprises a first conductive layer, a barrier layer and a second conductive layer which are stacked in sequence; wherein the first conductive layer includes a first polysilicon layer, a first metal layer and a second polysilicon layer, wherein the first polysilicon layer is adjacent to the substrate and the second polysilicon layer is contiguous to the barrier layer; and wherein the first metal layer is located between the first polysilicon layer and the second polysilicon layer. The gate structure of the embodiments of the application has a straight profile and an excellent electrical performance.

A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions . Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.

A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried bus having a bus conductive filler in a bus trench, where the bus conductive filler is electrically coupled to the gate electrode. The bus conductive filler is surrounded by the gate electrode. The gate trench intersects the bus trench in the semiconductor substrate. The gate electrode includes polysilicon. The bus conductive filler includes tungsten. The semiconductor structure also includes an adhesion promotion layer interposed between the bus conductive filler and the gate electrode, where the adhesion promotion layer includes titanium and titanium nitride. The semiconductor structure also includes a dielectric layer covering the gate electrode over the semiconductor substrate, where the buried bus has a coplanar top surface with the dielectric layer.

A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions. Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.

A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, a gate electrode, an interlayer insulating film, and a gate interconnection. The silicon carbide substrate includes: a first impurity region; a second impurity region provided on the first impurity region; and a third impurity region provided on the second impurity region so as to be separated from the first impurity region. A trench has a side portion and a bottom portion, the side portion extending to the first impurity region through the third impurity region and the second impurity region, the bottom portion being located in the first impurity region. When viewed in a cross section, the interlayer insulating film extends from above the third impurity region to above the gate electrode so as to cover the corner portion.

A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried bus having a bus conductive filler in a bus trench, where the bus conductive filler is electrically coupled to the gate electrode. The bus conductive filler is surrounded by the gate electrode. The gate trench intersects the bus trench in the semiconductor substrate. The gate electrode includes polysilicon. The bus conductive filler includes tungsten. The semiconductor structure also includes an adhesion promotion layer interposed between the bus conductive filler and the gate electrode, where the adhesion promotion layer includes titanium and titanium nitride. The semiconductor structure also includes a dielectric layer covering the gate electrode over the semiconductor substrate, where the buried bus has a coplanar top surface with the dielectric layer.

A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate. A first insulating film is around the fin-shaped semiconductor layer and a pillar-shaped semiconductor layer is on the fin-shaped semiconductor layer. A gate insulating film is around the pillar-shaped semiconductor layer. A metal gate electrode is around the gate insulating film and a metal gate line is connected to the metal gate electrode. A metal gate pad is connected to the metal gate line, and a width of the metal gate electrode and a width of the metal gate pad is larger than a width of the metal gate line.

A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, a gate electrode, an interlayer insulating film, and a gate interconnection. The silicon carbide substrate includes: a first impurity region; a second impurity region provided on the first impurity region; and a third impurity region provided on the second impurity region so as to be separated from the first impurity region. A trench has a side portion and a bottom portion, the side portion extending to the first impurity region through the third impurity region and the second impurity region, the bottom portion being located in the first impurity region. When viewed in across section, the interlayer insulating film extends from above the third impurity region to above the gate electrode so as to cover the corner portion.