An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.

A semiconductor device includes channel members vertically stacked, a gate dielectric layer wrapping around each of the channel members, a first work function (WF) layer disposed over the gate dielectric layer and wrapping around each of the channel members, a first WF isolation layer disposed over the first WF layer, a second WF layer disposed over the first WF isolation layer, a second WF isolation layer disposed over the second WF layer, and a metal fill layer disposed over the second WF isolation layer. The first WF layer has a uniform thickness. The second WF isolation layer is a nitride-containing layer.

In a thin-film transistor device, an inorganic insulating layer covers the via wall of a via, an active layer is disposed on a first electrode, the inorganic insulating layer, and a second electrode, a gate insulating layer covers the active layer, and a gate is disposed on a side of the gate insulating layer away from the via wall of the via, where the first electrode, the second electrode, and the inorganic insulating layer have the same conductive element.

A method includes forming a p-type transistor. The method includes forming a gate dielectric on a semiconductor region, and depositing a p-type work-function layer on the gate dielectric. The p-type work-function layer includes a metal nitride, which includes a first metal and a second metal. An n-type work-function layer is deposited over the p-type work-function layer. A p-type source/drain region is formed aside of the semiconductor region.

A semiconductor device may include a semiconductor substrate including first and second regions, a first gate structure on the first region, and a second gate structure on the second region. Each of the first and second gate structures may include a metal pattern, a high-k dielectric pattern between the semiconductor substrate and the metal pattern, and a work-function layer between the high-k dielectric pattern and the metal pattern. The work-function layer of the first gate structure may include a first metal element in the metal pattern of the first gate structure and a dipole material in the high-k dielectric pattern of the first gate structure, and the work-function layer and the high-k dielectric pattern in the second gate structure may include a metal oxide material. In the second gate structure, an oxygen content in the work-function layer may be higher than that in the high-k dielectric pattern.

A HEMT device comprises a trench-source contact which includes a first conductive portion and a second conductive portion superimposed on the first conductive portion. The first conductive portion is of a metal material which has a work function value lower than the work function value of the metal material of the second conductive portion.

A semiconductor device structure and methods of forming the same are described. The structure includes a first gate structure disposed over a substrate in an active device region, an insulating material disposed over the substrate in a passive device region, a resistor structure disposed over the insulating material in the passive device region, a first conductive contact electrically connected to the resistor structure, a second conductive contact disposed over the resistor structure, and a dielectric layer in contact with the second conductive contact and the resistor structure.

A semiconductor device includes channel structures extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, intersecting the first horizontal direction, bit lines extending in a vertical direction with each of the bit lines contacting a first end of a respective channel structure, a gate electrode extending in the second horizontal direction and surrounding the channel structures, gate dielectric layers with each gate dielectric layer between a respective channel structure and the gate electrode, and information storage structures extending in the vertical direction with each information storage structure contacting a second end of a respective channel structure that is opposite the first end of the respective channel structure. The gate electrode includes first conductive patterns with each first conductive pattern surrounding a respective channel structure, and a second conductive pattern surrounding the first conductive patterns.

A semiconductor memory device includes a first word line extending on a substrate in a first direction parallel with an upper surface of the substrate; a first semiconductor pattern including a first impurity region, a first channel region, and a second impurity region, wherein the first semiconductor pattern intersects the first word line and extends in a second direction parallel with the upper surface of the substrate and intersects the first direction; a first bit line extending in a third direction perpendicular to the upper surface of the substrate, wherein the first bit line is electrically connected to the first impurity region; and a data storage element that is electrically connected to the second impurity region, wherein the first word line includes a first conductive pattern including a plurality of grains, and wherein a crystal direction of the plurality of grains is parallel with the upper surface of the substrate.

The present disclosure relates to a gate all around (GAA) device made based on a GAA transistor structure that comprises a stack of multiple semiconductor channel layers and one or more first gate layers alternatingly arranged along a first direction. Each channel layer is encapsulated by a gate dielectric layer, and each first gate layer is arranged between two channel layers following another. The GAA transistor structure further comprises two second gate layers sandwiching the stack in a second direction and connected to the first gate layers. Each first gate layer is made of a first work function metal structure and each second gate layer is made of a second work function metal structure that is different from the first work function metal structure. Each first gate layer has a first thickness and each second gate layer has a second thickness larger than the first thickness.