Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.

Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

A semiconductor device can include: a substrate; a well region located in the substrate and having a first doping type; a body region located in the substrate and having a second doping type that is opposite to the first doping type; a source region located in the body region and having the first doping type; a drain region located in the well region and having the first doping type; an isolation structure located on the substrate and between the drain region and the source region; and a gate structure located on the isolation structure and including a first gate region and a second gate region, where the first gate region is of the first doping type, and the second gate region is of the second doping type.

An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (ESL) over the semiconductor substrate and the first gate, the first ESL having a curved top surface, and a first inter-layer dielectric (ILD) on the first ESL, the first ILD having a curved top surface. The semiconductor device further comprises a second ESL on the first ILD, the second ESL having a curved top surface, and a second ILD on the second ESL.

A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.

A semiconductor device includes a gate structure having a gate conductor and a sidewall spacer. A partial dielectric cap is formed on the gate conductor and extends less than a width of the gate conductor. A self-aligned contact is formed adjacent to the sidewall spacer of the gate structure and is electrically isolated from the gate conductor by the partial dielectric cap and the sidewall spacer.

A semiconductor device includes a substrate and a gate dielectric layer on the substrate. The gate dielectric layer includes a single metal oxide layer. The semiconductor device includes a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line. The gate electrode stack includes a work function layer covering the sidewall and the bottom surface of the metal filling line. The gate electrode stack includes a capping layer in contact with the gate dielectric layer between sidewalls of the gate dielectric layer and sidewalls of the work function layer. The capping layer includes TaC and at least one of TiN or TaN. The gate electrode stack includes a barrier layer interposed between the capping layer and the sidewalls of the work function layer. The barrier layer comprises TaC and WN, and the barrier layer is in contact with the capping layer.

A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

A field oxide film lies extending from the underpart of a gate electrode to a drain region. A plurality of projection parts projects from the side face of the gate electrode from a source region side toward a drain region side. The projection parts are arranged side by side along a second direction (direction orthogonal to a first direction along which the source region and the drain region are laid) in plan view. A plurality of openings is formed in the field oxide film. Each of the openings is located between projection parts adjacent to each other when seen from the first direction. The edge of the opening on the drain region side is located closer to the source region than the drain region. The edge of the opening on the source region side is located closer to the drain region than the side face of the gate electrode.