A display device may include a pixel circuit layer. A first electrode and a second electrode may be on the pixel circuit layer and spaced from each other. A first insulating layer may be on the pixel circuit layer, the first electrode, and the second electrode. A conductive pattern may be on the first insulating layer and electrically insulated from the first electrode and the second electrode. The bank may be on the conductive pattern. Light emitting elements may be located on the first insulating layer between the first electrode and the second electrode, and electrically coupled to the first electrode and the second electrode.

A terahertz module includes: a terahertz chip which includes an active device which emits a terahertz wave; and a dielectric substrate coupled to the terahertz chip. The terahertz chip includes a semiconductor substrate. The active device is disposed on an upper surface of the semiconductor substrate. A cutout is formed in a portion of a first side surface, among a plurality of side surfaces of the dielectric substrate, the cutout extending from an upper side of the first side surface to a lower side of the first side surface. The terahertz chip is fit into the cutout in such a direction that the upper surface of the semiconductor substrate is parallel to the first side surface and the semiconductor substrate is arranged in a bottom side of the cutout.

In accordance with aspects of the present technology, a unique charge carrier transfer process from c-plane InGaN to semipolar-plane InGaN formed spontaneously in nanowire heterostructures can effectively reduce the instantaneous charge carrier density in the active region, thereby leading to significantly enhanced emission efficiency in the deep red wavelength. Furthermore, the total built-in electric field can be reduced to a few kV/cm by cancelling the piezoelectric polarization with spontaneous polarization in strain-relaxed high indium composition InGaN/GaN heterostructures. An ultra-stable red emission color can be achieved in InGaN over four orders of magnitude of excitation power range. Accordingly, aspects of the present technology advantageously provide a method for addressing some of the fundamental issues in light-emitting devices and advantageously enables the design of high efficiency and high stability optoelectronic devices.

A tunable metamaterial has a two dimensional array of resonant annular ring elements; and a plurality of voltage controllable electrical tuning elements disposed in or adjacent openings in each of said ring elements, each of said voltage controllable electrical tuning element ohmically contacting portions of only one of said ring elements. The voltage controllable electrical tuning elements may comprise highly doped semiconductor tunnel diodes, or the charge accumulation layer at the semiconductor/insulator interface of a metal-insulator-semiconductor structure, or nanoelectromechanical (NEMs) capacitors. The tunable metamaterial may be used, for example, in an optical beam steering device using the aforementioned tunable optical metamaterial in which a free-space optical beam is coupled into a receiving portion of a plane of the optical metamaterial and is steered out of a transmitter portion of the plane of the optical metamaterial in controllable azimuthal and elevational directions. The tunable metamaterial additionally has other applications.

The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material. The anode is configured such that the second portion is horizontally located between the anode and the cathode and the dielectric material is configured to pinch off the 2DEG layer in a reverse biased configuration of the device. The device further includes a passivation area formed between the anode and the cathode to horizontally separate the anode and the cathode from each other.

A power semiconductor device includes a first contact, a second contact, and a semiconductor volume disposed between the first contact and the second contact. The semiconductor volume includes an n-doped field stop layer configured to spatially delimit an electric field that in the semiconductor volume during operation of the power semiconductor device, a heavily p-doped zone and a neighboring heavily n-doped zone, which together form a tunnel diode. The tunnel diode is located in the vicinity of, or adjacent to, or within the field stop layer. The tunnel diode is configured to provide protection against damage to the device due to a rise of an electron flow in an abnormal operating condition, by the fast provision of holes. Further, a method for producing such devices is provided.

In one embodiment, a device includes a substrate having a top surface and cavity that defines generally vertical walls, a thin film of material that has been deposited on the walls of the cavity, and a further material that fills the cavity, wherein a top edge of the thin film is exposed and forms a trace that is flush with the top surface of the substrate and has substrate material on one side and the further material on the other side.

A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.

In one aspect, a diode comprises: a semiconductor layer having a first side and a second side opposite the first side, the semiconductor layer having a thickness between the first side and the second side, the thickness of the semiconductor layer being based on a mean free path of a charge carrier emitted into the semiconductor layer; a first metal layer deposited on the first side of the semiconductor layer; and a second metal layer deposited on the second side of the semiconductor layer.

A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.