Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.

One or more systems, devices and/or methods provided herein relate to a device that can facilitate generation of a pulse to affect a qubit and to a method that can facilitate fabrication of a semiconductor device. The semiconductor device can comprise an RTD and an FET co-integrated in a common layer extending along a substrate. A method for fabricating the semiconductor device can comprise applying, at a substrate layer, a template structure comprising an opening, a cavity and a seed structure comprising a seed material and a seed surface, and sequentially growing along the substrate a plurality of diode layers of an RTD and a plurality of transistor layers of an FET within the cavity of the template structure from the seed surface, wherein the RTD and FET are co-integrated along the substrate.

A compound transistor comprises a first transistor structure and a second transistor structure. The first transistor structure includes a collector layer, a base layer on the collector layer, an emitter layer on a first portion of the base layer, and a base metal contact on a second portion of the base layer. The second transistor structure includes a channel layer directly on a first portion of the emitter layer and a barrier layer on the channel layer. A plurality of electrodes including a source, a gate, and a drain are formed on the barrier layer such that the source is electrically coupled to the base metal contact.

A method of manufacturing a semiconductor device, including: forming a first electrode film at a surface of a semiconductor wafer, the first electrode film having a convex defect at a surface thereof; covering the surface of the first electrode film with a resist film and inducing a break in the resist film at a portion corresponding to the convex defect, thereby generating a resist defect portion from which the convex defect is exposed; etching the convex defect exposed from the resist defect portion; removing the resist film after the etching; forming a second electrode film at the surface of the first electrode film after the removal of the resist film, thereby forming a surface electrode constituted by the first electrode film and the second electrode film; and patterning the surface electrode.

The reverse-conducting IGBT device is formed in a die having a substrate of a first conductivity type accommodating an IGBT in a first portion and a diode in a second portion. The IGBT has a body structure; a source region; a trench-gate region; a first contact structure; and an emitter region, of the second conductivity type. The diode has an anode region, of the second conductivity type, facing the first main surface; and a second contact structure, on the first main surface and in direct electrical contact with the anode region. The second contact structure is coupled with the first contact structure and is by a barrier layer extending above the first main surface of the substrate, in contact with the anode region, and by a diode contact plug, of metal, above and in contact with the barrier layer.

We describe a smart high voltage/power III-nitride semiconductor based diode or rectifier comprising first and second terminals, and further comprising an active device (e.g. a transistor such as a GaN HEMT transistor), a sensing device (e.g. a sensing diode/transistor), a sensing load (e.g. a resistor), wherein the smart high voltage/power III-nitride semiconductor based diode or rectifier is configured to output a sensing signal corresponding a current through the sensing device and/or a voltage drop across the sensing load, wherein the sensing signal is indicative of a current flowing between the first and second terminal when a bias is applied between the first and second terminals.

Trench-gate MOSFETs use a N+ SiC substrate with a N SiC drift layer. A Si wafer is bonded to the top of the SiC wafer, forming a Si/SiC heterojunction at the interface. Gate trenches are formed in the Si layer, oxidized, and filled with a conductor. Since the gate oxide is only in contact with the Si, and not the SiC, there is no problem with carbon at the gate oxide interface. Also, since the MOSFET is formed in the Si layer, electron mobility near the gates is high. JFET channel regions in the SiC layer pinch off during short circuit, high current conditions to limit drain current and thus achieve a higher short circuit withstand time capability. At the Si/SiC interface, a thin, highly doped n-type layer is formed in the SiC layer that allows tunneling current flowing through the barrier to lower the voltage drop across the heterojunction.

The disclosure relates to a semiconductor device (100), comprising: a die layer (110) comprising a top surface and a bottom surface opposing the top surface; wherein the die layer (110) forms a plurality of unit cells (120) arranged side-by-side across the top surface of the die layer (110), wherein each unit cell (120) comprises a sub cell of a first type (120a) and a sub cell of a second type (120b) which are both integrated in the unit cell (120), wherein the sub cell of the first type (120a) comprises a first electrode (121), a second electrode (122) and a third electrode (123) formed at the top surface of the die layer (110), a first one of the three electrodes (121, 122, 123) being arranged to enclose a second one of the three electrodes (121, 122, 123); and the first one and the second one of the three electrodes (121, 122, 123) being arranged to enclose a third one of the three electrodes (121, 122, 123); wherein the sub cells of the first type (120a) form high electron mobility transistor, HEMT, cells; and wherein the sub cells of the second type (120b) form Schottky Barrier Diode, SBD, cells.

Provided is a semiconductor device and method of manufacturing same, the semiconductor device including: a first active pattern which extends in a first direction; an isolation gate electrode on the first active pattern, wherein the isolation gate electrode includes an insulating material and extends in a second direction intersecting the first direction; an isolation capping pattern on the isolation gate electrode; a first recess in the isolation capping pattern and the isolation gate electrode; and a first insulating pattern inside the first recess, wherein the first insulating pattern includes a first liner film and a first filling film, wherein the first liner film includes a material different from the isolation gate electrode and the first filling film.

There is provided a semiconductor device with improved yield and performance. The semiconductor device includes a substrate including a first region and a second region and having a first conductivity type, first and second active patterns spaced apart by a first pitch, on the first region, a first gate structure intersecting the first and second active patterns, first epitaxial patterns each having a second conductivity type, different from the first conductivity type, and receiving the same voltage level, on both sides of the first gate structure on each of the first and second active patterns, third and fourth active patterns spaced apart by a second pitch, on the second region, a second gate structure intersecting the third and fourth active patterns, and second epitaxial patterns each having the second conductivity type, on the sides of the second gate structure on each of the third and fourth active patterns, wherein the first pitch is n times the second pitch (where n is a natural number of 2 or greater), and no epitaxial pattern having the second conductivity type is disposed between the first and second active patterns