Techniques to form semiconductor device conductive interconnections. In an example, an integrated circuit includes a recessed via and a conductive bridge between a top surface of the recessed via and an adjacent source or drain contact. A transistor device includes a semiconductor material extending from a source or drain region, a gate structure over the semiconductor material, and a contact on the source or drain region. Adjacent to the source or drain region, a deep via structure extends in a vertical direction through an entire thickness of the gate structure. The via structure includes a conductive via that is recessed below a top surface of the conductive contact. A conductive bridge extends between the contact and the conductive via such that the conductive bridge contacts a portion of the contact and at least a portion of a top surface of the conductive via.

A semiconductor device includes a substrate that includes a first surface and a second surface, a first source/drain pattern disposed on the first surface of the substrate, a second source/drain pattern disposed on the first surface of the, a first source/drain contact disposed on the first source/drain pattern and connected to the first source/drain pattern, a second source/drain contact disposed on the second source/drain pattern and connected to the second source/drain pattern, a rear wiring line disposed on the second surface of the substrate, a first contact connection via that connects the rear wiring line with the first source/drain contact, a second contact connection via that connects the rear wiring line with the second source/drain contact and is spaced apart from the first contact connection via, and an air gap structure disposed between the first contact connection via and the second contact connection via.

A continuous metal on diffusion edge (CMODE) may be used to form a CMODE structure in a semiconductor device after a replacement gate process that is performed to replace the polysilicon dummy gate structures of the semiconductor device with metal gate structures. The CMODE process described herein includes removing a portion of a metal gate structure (as opposed to removing a portion of a polysilicon dummy gate structure) to enable formation of the CMODE structure in a recess left behind by removal of the portion of the metal gate structure.

A semiconductor device and an isolation structure and a contact etch stop layer thereof are provided. According to an embodiment of the present disclosure, a semiconductor device is provided, which includes a first dielectric layer and a second dielectric layer. The first dielectric layer is deposited on the sidewall of an active device or formed in a trench of a gate structure. The second dielectric layer covers the first dielectric layer, wherein the dielectric constant of the first dielectric layer is between 2 and 2.5, and the dielectric constant of the second dielectric layer is less than or equal to 4. In some embodiments, a dielectric bilayer is composed of amorphous boron nitride and crystalline boron nitride.

Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

Design of overlay-based front end defect quick turn test chip is described. In an example, an integrated circuit structure includes a device layer including a vertical stack of horizontal nanowires or a fin, a gate electrode over the vertical stack of horizontal nanowires or the fin, a conductive trench contact adjacent to the gate electrode, and a dielectric sidewall spacer between the gate electrode and the conductive trench contact. The integrated circuit structure also includes a metallization layer immediately above the device layer, the metallization layer including a first test pad and a second test pad.

A method includes providing a substrate, an isolation structure, a semiconductor fin having a stack of first and second semiconductor layers, a dummy gate, and outer spacers on opposing sidewalls of the dummy gate; etching the semiconductor fin to form source/drain (S/D) trenches; etching the second semiconductor layers from the S/D trenches to form gaps vertically between the first semiconductor layers; forming inner spacers in the gaps; epitaxially growing S/D features in the S/D trenches; forming an inter-layer dielectric layer over the S/D features; etching the dummy gate and the outer spacers to form a gate-end trench away from the semiconductor fin and over the isolation structure; and forming a gate-end dielectric feature filling the gate-end trench, wherein a dielectric constant of the gate-end dielectric feature is higher than both a dielectric constant of the outer spacers and a dielectric constant of the inner spacers.

A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. A first wet etching process is performed by using a first etching solution, to clean a surface of the metal layer, wherein the first etching solution contains a base and a first oxidant. At least one cycle is performed. Each cycle includes a second wet etching process and a cleaning process. The second wet etching process is performed by using a second etching solution, to remove the metal layer, wherein the second etching solution contains an acid and a second oxidant. A cleaning process is performed.

Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.