In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.

A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.

A semiconductor device with a high on-state current is provided. A transistor included in the semiconductor device includes a first insulator; a first semiconductor layer over the first insulator; a second semiconductor layer including a channel formation region over the first semiconductor layer; a first conductor and a second conductor over the second semiconductor layer; a second insulator over the second semiconductor layer and between the first conductor and the second conductor; and a third conductor over the second insulator. In a cross-sectional view in a channel width direction of the transistor, the third conductor covers a side surface and a top surface of the second semiconductor layer. The second semiconductor layer has a higher permittivity than the first semiconductor layer. In the cross-sectional view in the channel width direction of the transistor, a length of an interface between the first semiconductor layer and the second semiconductor layer is greater than or equal to 1 nm and less than or equal to 20 nm, and a length from a bottom surface of the second semiconductor layer to a bottom surface of the third conductor in a region not overlapping with the second semiconductor layer is larger than a thickness of the second semiconductor layer.

A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a CMOS transistor area, and a resistor area. A polysilicon layer is deposited to provide a polysilicon gate area for MOS transistors in the CMOS transistor area, over the BSD class device area, and over the field dielectric for providing a polysilicon resistor in the resistor area. A first mask pattern is formed on the polysilicon layer. Using the first mask pattern, first implanting (I.sub.1) of the polysilicon resistor providing a first projected range (R.sub.P1)<a thickness of the polysilicon layer and second implanting (I.sub.2) providing a second R.sub.P(R.sub.P2), where R.sub.P2>R.sub.P1. I.sub.2 provides a CMOS implant into the semiconductor surface layer in the CMOS transistor area and/or a BSD implant into the semiconductor surface layer in the BSD area.

A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.

A method of microfabrication includes forming an initial vertical channel structure of semiconductor material protruding from a surface of a substrate such that the initial vertical channel structure has a current flow path that is perpendicular to the surface of the substrate. The initial vertical channel structure is segmented lengthwise into a plurality of independent vertical channel structure segments, each vertical channel structure segment having a respective current flow path that is perpendicular to the surface of the substrate.

Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

This application is directed to a low cost IC solution that provides Super CMOS microelectronics macros. Hereinafter, SCMOS refers to Super CMOS and Schottky CMOS. SCMOS device solutions includes a niche circuit element, such as complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co, Ti, Ni or other metal atoms or compounds) to P- and N- Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros are composed of diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form (i) generic logic gates, (ii) functional blocks of microprocessors and microcontrollers such as but not limited to data paths, multipliers, muliplier-accumaltors, (ii) memory cells and control circuits of various types (SRAM's with single or multiple read/write port(s), binary and ternary CAM's), (iii) multiplexers, crossbar switches, switch matrices in network processors, graphics processors and other processors to implement a variety of communication protocols and algorithms of data processing engines for (iv) Analytics, (v) block-chain and encryption-based security engines (vi) Artificial Neural Networks with specific circuits to emulate or to implement a self-learning data processor similar to or derived from the neurons and synapses of human or animal brains, (vii) analog circuits and functional blocks from simple to the complicated including but not limited to power conversion, control and management either based on charge pumps or inductors, sensor signal amplifiers and conditioners, interface drivers, wireline data transceivers, oscillators and clock synthesizers with phase and/or delay locked loops, temperature monitors and controllers; all the above are built from discrete components to all grades of VLSI chips. Solar photovoltaic electricity conversion, bio-lab-on-a-chip, hyperspectral imaging (capture/sensing and processing), wireless communication with various transceiver and/or transponder circuits for ranges of frequency that extend beyond a few 100 MHz, up to multi-THz, ambient energy harvesting either mechanical vibrations or antenna-based electromagnetic are newly extended or nacent fields of the SCMOS IC applications.