A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

A method of microfabrication includes providing a substrate having an existing pattern of features formed within a first layer, depositing a selective attachment agent on the substrate, wherein the selective attachment agent attaches to the features and includes a solubility-shifting agent, depositing a first resist on the substrate, activating the solubility-shifting agent such that a portion of the first resist over the features becomes soluble to a first developer, developing the first resist using the first developer such that a relief pattern having openings that expose the features of the existing layer is formed, growing a selective growth material on the features and within the openings of the relief pattern to provide self-aligned selective growth features, removing the first resist, depositing a fill layer on the substrate, and repeating the steps a predetermined number of times to provide a stacked device including a predetermined number of levels.

A semiconductor device that has two transistors and a source/drain contact. The first transistor has a layer of semiconductor material that acts as a channel, a structure that serves as a gate and wraps around the semiconductor channel layer, and two epitaxy structures on either end of the semiconductor channel layer that function as the source and drain. The second transistor is situated above the first transistor and has similar components, including a semiconductor channel layer, gate structure, and source/drain epitaxy structures. The connection between the first and second source/drain epitaxy structures is made by a source/drain contact that passes through one of the second source/drain epitaxy structures. This contact is made up of a metal plug and a metal liner that lines the plug.

Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.

A semiconductor device, includes a source and drain bottom epitaxial layer positioned on top of a dielectric substrate. A metal gate is positioned on top of the bottom epitaxial layer. A source and drain top epitaxial layer is positioned on top of the metal gate. A first and second semiconductor channel pass vertically from the source and drain top epitaxial layer through the metal gate to the source and drain bottom epitaxial layer. First and second metal contacts are conductively coupled to the first and second semiconductor channels. First and second metal vias are formed on a backside of the source and drain bottom epitaxial layer and arranged in conductive contact with the first and second semiconductor channels. A metal layer is formed on a backside of the first and second metal vias.

A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction.

Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.

An integrated circuit includes a driver cell and at least one transmission cell. The driver cell includes a first active area and a second active area, and a first conductive line coupled to the first active area and the second active area on a back side of the integrated circuit. The at least one transmission cell having a second cell height includes a third active area and a fourth active area, a second conductive line coupled to the third active area and the fourth active area on the back side of the integrated circuit, and a conductor coupled to the third active area and the fourth active area. The integrated circuit further includes a third conductive line coupled between the first conductive line and the second conductive line on the back side to transmit a signal between the driver cell and the at least one transmission cell.

Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.