A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.

An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor being an N-type transistor and including a first silicon-germanium layer on the substrate, and a first gate electrode on the first silicon-germanium layer, and a second transistor in the second region and including a second gate electrode, the second transistor not having a silicon-germanium layer between the substrate and the second gate electrode.

A two-dimensional heterostructure is synthesized by producing a patterned first two-dimensional material on a growth substrate. The first two-dimensional material is patterned to define at least one void through which an exposed region of the growth substrate is exposed. Seed molecules are selectively deposited either on the exposed region of the growth substrate or on the patterned first two-dimensional material. A second two-dimensional material that is distinct from the first two-dimensional material is then grown from the deposited seed molecules.

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

An embodiment is a structure including a first active device in a first region of a substrate, the first active device including a first layer of a two-dimensional (2-D) material, the first layer having a first thickness, and a second active device in a second region of the substrate, the second active device including a second layer of the 2-D material, the second layer having a second thickness, the 2-D material including a transition metal dichalcogenide (TMD), the second thickness being different than the first thickness.

A silicon germanium alloy (SiGe) fin having a first germanium content is provided within first and second device regions. Each SiGe fin is located on a sacrificial material stack and an oxide material surrounds each SiGe fin. A germanium layer is formed atop each SiGe fin within one of the device regions, while a SiGe layer having a second germanium content less than the first germanium content is formed atop each SiGe fin within the other device region. An exposed surface of each of the germanium layer and the SiGe layer is then bonded to a base substrate. The sacrificial material stack is removed and thereafter the oxide material is recessed to expose a portion of each SiGe fin in the first and second device regions. Each SiGe fin contacting the germanium layer compressively strained, and each SiGe fin contacting the SiGe layer is tensely strained.

A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.

Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the transistor channel may be disposed between the second barrier and the first barrier, and a bandgap of the transistor channel may be less than a bandgap of the first barrier and less than a bandgap of the second barrier. Other embodiments may be disclosed and/or claimed.

Provided is a two-dimensional large-area growth method for a chalcogen compound, the method including: depositing a film of a transition metal element or a Group V element on a substrate; thereafter, uniformly diffusing a vaporized chalcogen element, a vaporized chalcogen precursor compound or a chalcogen compound represented by MX.sub.2+ within the film; and, thereafter, forming a film of a chalcogen compound represented by MX.sub.2 by forming the chalcogen compound represented by MX.sub.2 through post-heating.