A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.

The present application teaches, among other innovations, methods and circuits for operating a B-TRAN (double-base bidirectional bipolar junction transistor). A base drive circuit is described which provides high-impedance drive to the base contact region on whichever side of the device is operating as the collector (at a given moment). (The B-TRAN, unlike other bipolar junction transistors, is controlled by applied voltage rather than applied current.) The preferred implementation of the drive circuit is operated by control signals to provide diode-mode turn-on and pre-turnoff operation, as well as a hard ON state with a low voltage drop (the transistor-ON state). In some but not necessarily all preferred embodiments, an adjustable low voltage for the gate drive circuit is provided by a self-synchronizing rectifier circuit. Also, in some but not necessarily all preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while the base current at that terminal is monitored, so that no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in a B-TRAN.

A lateral p-n diode in the center of and surrounded by a vertical Silicon-Controlled Rectifier (SCR) forms an Electro-Static-Discharge (ESD) protection structure. The lateral p-n diode has a cross-shaped P+ diode tap with four rectangles of N+ diode regions in each corner of the cross. A P-well under the P+ diode tap is also an anode of a vertical PNPN SCR that has a deep N-well in a P-substrate. The deep N-well surrounds the lateral diode. Triggering MOS transistors are formed just beyond the four ends of the cross shaped P+ diode tap. Each triggering MOS transistor has N+ regions at the edge of the deep N-well and in the P-substrate that act as the cathode terminals. A deep P+ implant region under the N+ region at the edge of the deep N-well decreases a trigger voltage of the vertical SCR.

A semiconductor device is provided. The semiconductor device includes an avalanche photodiode unit and a thyristor unit. The avalanche photodiode unit is configured to receive incident light to generate a trigger current and comprises a wide band-gap semiconductor. The thyristor unit is configured to be activated by the trigger current to an electrically conductive state. A semiconductor device and a method for making a semiconductor device are also presented.

A combined semiconductor controlled circuit (CSCC) includes a semiconductor controlled switch (SCS). The SCS includes anode, cathode, anode gate and cathode gate terminals connected to P.sub.1 anode, N.sub.2 cathode, N.sub.1 anode gate and P.sub.2 cathode gate layers. The SCS also includes P-N junctions between P.sub.1 anode and N.sub.1 anode gate layers, N.sub.1 anode gate and P.sub.2 cathode gate layers and P.sub.2 cathode gate and N.sub.2 cathode layers. The CSCC also includes a Zener diode having a current path flowing from the cathode terminal to the anode gate terminal, a feedback resistor connecting cathode and cathode gate terminals and a substrate. A solid-state spark chamber includes a CSCC, a DC bias voltage source and an RC load having a parallel-connected load resistor and capacitor. The solid-state spark chamber also includes a plurality of measurement terminals and a ground. A method of making a solid-state spark chamber includes connecting the above components.

A lateral p-n diode in the center of and surrounded by a vertical Silicon-Controlled Rectifier (SCR) forms an Electro-Static-Discharge (ESD) protection structure. The lateral p-n diode has a cross-shaped P+ diode tap with four rectangles of N+ diode regions in each corner of the cross. A P-well under the P+ diode tap is also an anode of a vertical PNPN SCR that has a deep N-well in a P-substrate. The deep N-well surrounds the lateral diode. Triggering MOS transistors are formed just beyond the four ends of the cross shaped P+ diode tap. Each triggering MOS transistor has N+ regions at the edge of the deep N-well and in the P-substrate that act as the cathode terminals. A deep P+ implant region under the N+ region at the edge of the deep N-well decreases a trigger voltage of the vertical SCR.

An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.

A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F.sup.2. This array of threshold switching devices is suitable for a variety of memory or other applications including PRAM, MRAM, RRAM, FRAM, OPT-RAM and 3-D memory.

Fin field-effect transistor (FinFET) thyristors for protecting high-speed communication interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a first ESD protection unit in a P-type semiconductor substrate to protect a first circuit. The first ESD protection unit includes first and second N-type and P-type well regions. The first N-type and P-type doped regions are in the first N-type well region. The second N-type and P-type doped regions are in the first P-type and second N-type well regions. The third N-type and P-type doped regions are in the second P-type well region. The first P-type and the third N-type doped regions are electrically connected to a common bus electrically connected to power supply and ground terminals of the first circuit. The first N-type and the second P-type doped regions are electrically connected to the power supply terminal. The second N-type and the third P-type doped regions are electrically connected to the ground terminal.