The present disclosure provides a semiconductor device including a diode. The semiconductor device includes: a semiconductor substrate; an n-type diffusion region selectively formed in a surface layer portion of a p-type epitaxial layer; an n-type buried layer sandwiched between the semiconductor substrate and the n-type diffusion region and having an impurity concentration greater than that of the n-type diffusion region; a p-type anode contact region formed in a surface layer portion of a first main surface of the semiconductor substrate; an n-type first cathode contact region formed in a surface layer portion of the n-type diffusion region and in a surface layer portion of the first main surface; a p-type well region extending along a depth direction from the first main surface outside the first cathode contact region to reach the n-type buried layer, dividing the n-type diffusion region along a direction along the first main surface.

Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).

A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is within the p-body region providing a drain extension region, and a gate dielectric layer is formed over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region, and a patterned gate electrode on the gate dielectric. A DWELL region is within the p-body region, sidewall spacers are on sidewalls of the gate electrode, a source region is within the DWELL region, and a drain region is within the NDRIFT region. The p-body region includes a portion being at least one 0.5 m wide that has a net p-type doping level above a doping level of the p-epi layer and a net p-type doping profile gradient of at least 5/m.

A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is within the p-body region providing a drain extension region, and a gate dielectric layer is formed over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region, and a patterned gate electrode on the gate dielectric. A DWELL region is within the p-body region, sidewall spacers are on sidewalls of the gate electrode, a source region is within the DWELL region, and a drain region is within the NDRIFT region. The p-body region includes a portion being at least one 0.5 m wide that has a net p-type doping level above a doping level of the p-epi layer and a net p-type doping profile gradient of at least 5/m.

Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

In one embodiment, a RESURF structure between a source and a drain in a lateral MOSFET is formed in a trench having a flat bottom surface and angled sidewalls toward the source. Alternating P and N-type layers are epitaxially grown in the trench, and their charges balanced to achieve a high breakdown voltage. In the area of the source, the ends of the P and N-layers angle upward to the surface under the lateral gate and contact the body region. Thus, for an N-channel MOSFET, a positive gate voltage above the threshold forms a channel between the source and the N-layers in the RESURF structure as well as creates an inversion of the ends of the P-layers near the surface for low on-resistance. In another embodiment, the RESURF structure is vertically corrugated by being formed around trenches, thus extending the length of the RESURF structure for a higher breakdown voltage.

A method forms an integrated circuit, by steps including, in a first implant, forming in a semiconductor substrate a first and second region of a first semiconductor type, each of the first and second region having a first dopant concentration; in a second implant, forming in the semiconductor substrate a third and fourth region of the first semiconductor type, the third region at least partially overlapping the first region and the fourth region at least partially overlapping the second region, each of the third and fourth region having a second dopant concentration different than the first dopant concentration; forming a transistor source within the first and third regions; and forming one of a diode anode or a diode cathode in the second and fourth regions.

An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

A new field-effect transistor (FET) based switch for use in/with high voltage precision instruments is provided. The switch can enable leakage compensation. A switch comprises a first FET in series with a second FET, and a buffer with an output terminal and an input terminal. The drain terminal of the first FET is connected to the source terminal of the second FET. The input terminal is coupled to the drain terminal of the second FET. At least one of: the first FET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the first FET; and, the second SFET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the second FET.

A semiconductor device includes a semiconductor chip including first and second main surfaces. A first semiconductor region of a first conductivity type is formed in the semiconductor chip near the first main surface. A second semiconductor region of a second conductivity type is formed closer to the second main surface than the first semiconductor region is. A trench structure includes a trench extending from the first main surface and partitioning the first semiconductor region into first and second regions. A control insulation film covers a wall of the trench. A control electrode is embedded in the trench with the control insulation film interposed to electrically connect the first and second regions. A third semiconductor region of the first conductivity type is formed closer to the second main surface than the second semiconductor region. The third semiconductor region and the trench structure sandwich the second semiconductor region.