A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.

Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

According to one embodiment, the insulating film is provided between the anode region and the cathode region in the surface of the second semiconductor region. The third semiconductor region is provided inside the second semiconductor region. The third semiconductor region covers a corner of the insulating film on the anode region side. The first electrode contacts the anode region and the third semiconductor region. The second electrode contacts the cathode region. The third electrode is provided on the insulating film and positioned on a p-n junction between the second semiconductor region and the third semiconductor region.

A MOSFET device having a single channel in a traditional dual-channel MOSFET cell layout. The invention uses both a split gate and single channel to improve the capacitance of the fabricated devices with minimal effect on the static performance. The MOSFET cell is on a substrate and has a first P-well and second P-well, with a gate formed over only a portion of the first P-well, the gate extending a predetermined distance but not over the second P-well. A single channel is then selectively created upon the application of a predetermined voltage to the gate. The second P-well structure can be used to create other devices, such as a Schottky diode or a P+ region.

This application is directed to integrating metal oxide semiconductor (MOS) transistors and Schottky barrier diodes (SBDs). An integrated planar semiconductor device includes a substrate, an SBD joining an SBD semiconductor and a barrier metal on the substrate, and a MOS transistor formed on the substrate and including a gate, a source, and a drain. A portion of the gate of the MOS transistor extends from the MOS transistor to the SBD and is in contact with the SBD semiconductor. In some implementations, the drain of the MOS transistor includes an extended drain structure. The SBD semiconductor includes a first semiconductor portion and a second semiconductor portion. A doping profile of the extended drain structure is substantially the same as that of the second semiconductor portion. A doping concentration of a channel region of the MOS transistor is substantially the same as that of the first semiconductor portion.

A 4H-SiC lateral bi-directional JBS diode integrated MOSFET (L-BID-JBSFET). The unit cell of the L-BiD-JBSFET is constructed by connecting two SiC lateral JBSFET unit cells back-to-back with a common-drain configuration. Alternate embodiments include SiC lateral MOSFET and SiC lateral JBSFET devices. A Schottky region can be integrated within a lateral MOSFET cell structure to form the JBSFET.

The semiconductor device includes a chip having side surface, and an ornamental pattern formed in the side surface. The chip includes a semiconductor layer of a first conductivity type, and the ornamental pattern includes a mark of a second conductivity type that is formed in a portion constituted of the semiconductor layer in the side surface. The side surface includes a first side surface extending in a first direction in plan view and a second side surface extending in a second direction intersecting the first direction in plan view, and the ornamental pattern includes at least one of mark formed in one or both of the first side surface and the second side surface.

An SiC semiconductor device includes an SiC layer of a first conductivity type that has a main surface, an active region set in an inner portion of the main surface, an outer peripheral region set in a peripheral edge portion of the main surface, and a column region of a second conductivity type that is formed in the SiC layer at an interval in a horizontal direction along the main surface and includes impurity regions positioned in both the active region and the outer peripheral region.

A silicon carbide semiconductor device includes: a dummy sense region; and a drift layer of a first conductivity type, wherein a MOSFET with a built-in SBD including a first well region of a second conductivity type connected to a source electrode is formed in an active region, a MOSFET with a built-in SBD including a second well region of a second conductivity type connected to a sense pad is formed in an active sense region, and a third well region of a second conductivity type which is not ohmic-connected to any of the source electrode and the sense pad is formed on an upper layer part of the n-type drift layer in the dummy sense region. A gate electrode of the MOSFET with the built-in SBD in the active region and the MOSFET with the built-in SBD in the active sense region is connected to a gate pad.