A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

A semiconductor device is provided including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.

A semiconductor device is provided including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.

A method forms an integrated circuit, by steps including forming a polysilicon layer having a first side over a semiconductor substrate having a top surface, forming over the semiconductor substrate a first resist layer having a second side spaced apart from the first side, forming a diode well extending into the semiconductor substrate between the first side and the second side, the diode well having a first conductivity type, forming over the semiconductor substrate a second resist layer having a third side, and forming a diode terminal extending into the semiconductor substrate between the first side and the third side, the diode terminal having an opposite second conductivity type and extending from the diode well along the top surface.

Disclosed is a circuit including a transistor with integrated circuitry for protection against damage due to an electrostatic discharge (ESD) event or other drain voltage (Vd) overstress condition. The transistor is an N-type field effect transistor (NFET) and includes a drain region, a source region connected to ground, and a gate connected to a first node. The first node is connected to receive an externally-generated gate bias voltage. A resistor-capacitor (RC)-triggered voltage clamp is connected in parallel with the transistor. Specifically, a resistor is connected between the source region and a second node and a capacitor is connected between the second node and the drain region. A first diode or series-connected first diodes is/are connected between the second node and the first node. Optionally, a resistor-diode (RD)-triggered voltage clamp is also connected in parallel with the transistor and shares the resistor and second node with the RC-triggered voltage clamp.