A combination structure of semiconductor deep trench devices includes: a deep trench insulator device, which includes at least one deep trench ring unit, wherein the deep trench ring unit includes: a deep trench ring, a first dielectric side wall layer and a first poly silicon fill region; and a deep trench capacitor device, which includes a plurality of deep trench capacitor units and a cathode, wherein each of the deep trench capacitor units includes: a deep trench hole; a second dielectric side wall layer; and a second poly silicon fill region. The deep trench hole is formed by etching a semiconductor substrate with a same etch process step with the deep trench ring. The first dielectric side wall layer and the second dielectric side wall layer is formed by a same oxide growth process step.

Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

A system and method for fabricating on-die metal-insulator-metal capacitors capable of maintaining a similar capacitance for design reuse across multiple semiconductor fabrication processes are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors. The MIM capacitors are formed between two signal nets. The integrated circuit includes multiple intermediate metal layers (or metal plates) formed between two signal nets. Subsequent semiconductor fabrication processes typically increase a number of metal plates that can be formed in the dielectric layer, such as an oxide layer, between two signal nets. To permit design reuse across multiple semiconductor fabrication processes, for a particular MIM capacitor designated to maintain a same capacitance, the additional metal plates for the particular MIM capacitor are formed as floating nets. Additionally, the same electrode plates of the particular MIM capacitor are used across the multiple semiconductor fabrication processes.

A capacitor structure and a forming method thereof are provided. The capacitor structure includes a substrate and a bottom electrode composite layer on the substrate. The bottom electrode composite layer includes a first electrode layer and a second electrode layer on the first electrode layer. An oxidation rate of a material of the second electrode layer is lower than an oxidation rate of a material of the first electrode layer. The capacitor structure also includes a dielectric structure layer on the bottom electrode composite layer.

An on-die-capacitor structure includes a first capacitor and a second capacitor. The first capacitor may have first and second terminals. The first and second terminals are directly connected to first and second power supply rail structures, respectively. The first power supply rail structure is different from the second power supply rail structure. The second capacitor may have third and fourth terminals. The second capacitor is connected in series between the second power supply rail structure and a third power supply rail structure. The third power supply rail structure is different from the first and second power supply rail structures. The third and fourth terminals are directly connected to the second and third power supply rail structures, respectively. The first capacitor may have a first capacitance and the second capacitor structure may have a second capacitance that is greater than the first capacitance.

A method for fabricating memory device includes the steps of: providing a substrate; forming a tunnel oxide layer on the substrate; forming a first gate layer on the tunnel oxide layer; forming a negative capacitance (NC) insulating layer on the first gate layer; and forming a second gate layer on the NC insulating layer. Preferably, the second gate layer further includes a work function metal layer on the NC insulating layer and a low resistance metal layer on the work function metal layer.

A semiconductor device and methods of formation are provided herein. A semiconductor device includes a conductor concentrically surrounding an insulator, and the insulator concentrically surrounding a column. The conductor, the insulator and the conductor are alternately configured to be a transistor, a resistor, or a capacitor. The column also functions as a via to send signals from a first layer to a second layer of the semiconductor device. The combination of via and at least one of a transistor, a capacitor, or a resistor in a semiconductor device decreases an area penalty as compared to a semiconductor device that has vias formed separately from at least one of a transistor, a capacitor, or resistor.

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer.

Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode.

A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench.