An integrated circuit (IC) device comprises a conductive contact at a surface of the IC device. A resistive element is coupled between the conductive contact and first circuitry. Second circuitry is coupled between the resistive element and the conductive contact. The second circuitry is further coupled with a supply line and comprises at least one of a diode or a power clamp. The resistive element is disposed in a first metallization layer of the IC device. A first dielectric layer is adjacent to the first metallization layer. A second metallization layer is adjacent to the first dielectric layer. A height of the first dielectric layer and the second metallization layer is a first distance. A zone overlaps the resistive element, and extends a second distance away from the resistive element. The zone is free of conductive material and the second distance is greater than the first distance.

A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.

The present disclosure relates to semiconductor devices. An example semiconductor device includes a first well region and a second well region isolated from each other by a first device isolation film; an NPN transistor provided by a first collector region formed in the first well region and including first conductivity-type impurities, and a first emitter region formed in the second well region and including the first conductivity-type impurities; a PNP transistor provided by a second emitter region formed in the first well region and including second conductivity-type impurities different from the first conductivity-type, and a second collector region formed in the second well region and including the second conductivity-type impurities; and an NMOS transistor including a source region and a drain region formed in the second well region and including the first conductivity-type impurities, and a gate structure disposed between the source region and the drain region.

A structure includes a first gate structure spaced from a second gate structure in a field effect transistor (FET) area of a substrate. A polysilicon resistor is in a space between the first gate structure and the second gate structure. The polysilicon resistor has a lower surface that is farther from the substrate than lower surfaces of the polysilicon bodies of the first and second gate structures. The polysilicon resistor may have a different polarity dopant compared to at least one of the polysilicon bodies of the first and second gate structures.

Integrated chips and methods of forming the same include forming a gate stack around a first semiconductor fin and a second semiconductor fin. The gate stack around the second semiconductor fin is etched away. An extrinsic base is formed around the second semiconductor fin in a region exposed by etching away the gate stack.

A semiconductor package in an embodiment includes a semiconductor device which has a first semiconductor element, a second semiconductor element, and a common first electrode between the first and second semiconductor elements. A second electrode is electrically connected to the first semiconductor element. A third electrode extends through the second semiconductor element and electrically connects to the first electrode. A fourth electrode is electrically connected to the second semiconductor element. A first terminal of the package is electrically connected to the third electrode. A second terminal of the package is electrically connected to the second electrode and the fourth electrode. An insulating material surrounds the semiconductor device.

The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a CMOS transistor area, and a resistor area. A polysilicon layer is deposited to provide a polysilicon gate area for MOS transistors in the CMOS transistor area, over the BSD class device area, and over the field dielectric for providing a polysilicon resistor in the resistor area. A first mask pattern is formed on the polysilicon layer. Using the first mask pattern, first implanting (I.sub.1) of the polysilicon resistor providing a first projected range (R.sub.P1)<a thickness of the polysilicon layer and second implanting (I.sub.2) providing a second R.sub.P(R.sub.P2), where R.sub.P2>R.sub.P1. I.sub.2 provides a CMOS implant into the semiconductor surface layer in the CMOS transistor area and/or a BSD implant into the semiconductor surface layer in the BSD area.

A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

An electronics apparatus including a first substrate having a first surface and a second surface, a first switch connected to a second switch and soldered in series on the first surface of the first substrate creating a connection to allow switching between the first switch and the second switch at high frequency, an insulation having a third surface attached to the second surface of the first substrate, and a second substrate having a pocket of low permittivity located between the first switch and the second switch on a fourth surface of the insulation, the fourth surface being opposite to the third surface where the first switch and the second switch are located.