An IGBT includes, in a single chip, an active region configured to conduct a forward load current between first and second load terminals at different sides of a semiconductor body. The active region is separated into at least first and second IGBT regions. At least 90% of the first IGBT region is configured to conduct, based on a first control signal, the forward load current. At least 90% of the second IGBT region is configured to conduct, based on a second control signal, the forward load current. A first MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the first IGBT region divided by a total lateral area of first IGBT region. A second MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the second IGBT region divided by a total lateral area of the second IGBT region. The second MOS-channel-conductivity-to-area-ratio amounts to less than 80% of the first MOS-channel-conductivity-to-area-ratio.

An RC IGBT includes, in a single chip, an active region configured to conduct both a forward load current and a reverse load current between a first load terminal at a front side of a semiconductor body of the RC IGBT and a second load terminal at a back side of the semiconductor body. The active region is separated into at least: an IGBT-only region, at least 90% of which is configured to conduct, based on a first control signal, only the forward load current; an RC IGBT region, at least 90% of which is configured to conduct the reverse load current and, based on a second control signal, the forward load current; and a hybrid region, at least 90% of which is configured to conduct, based on both the first control signal and the second control signal, the forward load current.

Described implementations provide wireless, surface mounting of at least two semiconductor devices on opposed surfaces of a leadframe, to provide an isolated, three-dimensional (3D) configuration. The described implementations minimize electrical failures, even for very high voltage applications, while enabling low inductance and high current. Resulting semiconductor device packages have mounting surfaces that provide desired levels of isolation and insulation, while still enabling straightforward mounting techniques, such as soldering, as well as high levels of thermal reliability.

A semiconductor device including a semiconductor substrate having an upper surface and a lower surface is provided. In a depth direction connecting the upper and lower surfaces of the semiconductor substrate, a donor concentration distribution includes a first donor concentration peak at a first depth, a second donor concentration peak at a second depth between the first donor concentration peak and the upper surface, a flat region between the first donor concentration peak and the second donor concentration peak, and a plurality of donor concentration peaks between the first donor concentration peak and the lower surface. The second donor concentration peak has a lower concentration than the first donor concentration peak. The donor concentration distribution in the flat region is substantially flat. The thickness of the flat region in the depth direction is 10% or more of the thickness of the semiconductor substrate.

A semiconductor apparatus includes a semiconductor substrate and a second electrode. Semiconductor substrate includes a device region and a peripheral region. An n.sup. drift region and second electrode extend from device region to peripheral region. An n buffer layer and a p collector layer are provided also in peripheral region. Peripheral region is provided with an n type region. N type region is in contact with second electrode and n buffer layer. The turn-off loss of the semiconductor apparatus is reduced.

Provided is a semiconductor device including: a semiconductor substrate including an active portion in which transistor portions and diode portions are alternately provided and provided with a plurality of trench portions extending in an extending direction of the transistor portion and the diode portion; an emitter electrode provided above a front surface of the semiconductor substrate; and a protective film of polyimide provided on an upper surface of the emitter electrode, wherein the diode portion includes a lifetime control region including a lifetime killer irradiated from a front surface side of the semiconductor substrate, wherein the active portion includes a protected region provided with the protective film and an unprotected region not provided with the protective film, and wherein the diode portion is included in the unprotected region and the protected region is included in the transistor portion.

A semiconductor device includes a chip that has a first main surface on one side and a second main surface on the other side, an IGBT region provided in an inner portion of the first main surface, an outer peripheral region provided in a peripheral edge portion of the first main surface, a first conductivity type well region formed in a surface layer portion of the first main surface in the outer peripheral region so as to define the IGBT region, an insulating film that covers the well region, a well connection electrode embedded in the insulating film so as to be connected to the well region, and a second conductivity type cathode region formed in a surface layer portion of the second main surface in the outer peripheral region so as to oppose the well connection electrode, and that forms a diode with the well region.

A semiconductor device is provided that maintains assembly and improves stress tolerance. The semiconductor device includes a plurality of trenches, a plurality of trench electrodes, an insulation film, and a first electrode. The trench electrodes are provided respectively inside the trenches. The insulation film covers two or more of the trench electrodes. The first electrode is provided on the insulation film. The insulation film has an opening provided between the two or more trench electrodes covered with the insulation film. The first electrode is provided on the semiconductor substrate to fill the opening. Each of the trench electrodes has an upper surface that includes a first recessed portion. The insulation film has an upper surface that includes a second recessed portion located immediately above the first recessed portion. The first electrode has an upper surface that includes a third recessed portion located immediately above the opening.

A p-type semiconductor region is formed in a front surface side of an n-type semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donors in the FS region include first, second, third and fourth peaks in order from a front surface to the rear surface. Each of the peaks has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum points of the first and second peaks are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak.

A semiconductor device includes a gate electrode embedded in each of a plurality of first trenches through an insulating film. The gate electrode includes a first gate electrode electrically connected to a first gate pad and a second gate electrode electrically connected to a second gate pad. A charge period and a discharge period of gate capacitance parasitic on the second gate electrode are shorter than a charge period and a discharge period of gate capacitance parasitic on the first gate electrode, respectively.