Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

A power semiconductor device is comprised of a plurality of zones having similar structure. Each of the zones may be characterized by a switching loss during transitions to a non-conducting state. The device is configured such that the switching loss is different between at least two of the zones. Further, the device is configured such that zones having greater switching losses transition to the non-conducting state before zones having lesser switching losses.

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

A switching circuit switches a first IGBT and a second IGBT. A control circuit is equipped with a first switching element that is configured to be able to control a gate current of the first IGBT, a second switching element that is configured to be able to control a gate current of the second IGBT, and a third switching element that is connected between an electrode of the first IGBT and an electrode of the second IGBT. The control circuit controls a turn on timing and turn off timing.

A switching circuit includes a wiring into which a parallel circuit of a first IGBT and a second IGBT is inserted, and a gate control circuit. The gate control circuit has a first switching element configured to control a gate potential of the first IGBT according to a potential of a second principal electrode, and a second switching element configured to control a gate potential of the second IGBT according to a potential of a fourth principal electrode. An output terminal of the control device is connected to the first switching element through a first switch and is connected to the second switching element through a second switch. The control device applies a control signal to the output terminal in a state where the first switch and the second switch are turned on when switching both of the first IGBT and the second IGBT.

A switching circuit switches a first IGBT and a second IGBT. A control circuit is equipped with a first switching element that is configured to be able to control a gate current of the first IGBT, a second switching element that is configured to be able to control a gate current of the second IGBT, and a third switching element that is connected between an electrode of the first IGBT and an electrode of the second IGBT. The control circuit controls a turn on timing and turn off timing.

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

An igniter is not provided with a depression IGBT and is configured such that a distance between a main IGBT and a sense IGBT is equal to or greater than 100 m and equal to or less than 700 m and preferably equal to or greater than 100 m and equal to or less than 200 m. The igniter is controlled such that, before the overcurrent of the main IGBT reaches a predetermined upper limit, a sense current of the sense IGBT is saturated. Therefore, it is possible to provide the igniter which has a small size and prevents the overshoot of a collector current of the main IGBT when a current is limited and an internal combustion engine ignition apparatus which includes the igniter, has a small size, and prevents an ignition error.

A power semiconductor device is comprised of a plurality of zones having similar structure. Each of the zones may be characterized by a switching loss during transitions to a non-conducting state. The device is configured such that the switching loss is different between at least two of the zones. Further, the device is configured such that zones having greater switching losses transition to the non-conducting state before zones having lesser switching losses.

A semiconductor device including a mesa portion formed on a front surface side of a semiconductor substrate; a floating portion formed on the front surface side of the semiconductor substrate; a trench formed surrounding the floating portion and separating the mesa portion from the floating portion; an electrode formed inside the trench; and an outside wiring portion formed along an arrangement direction of the mesa portion and the floating portion, outside the region surrounded by the trench. An edge of the outside wiring portion on the mesa portion and floating portion side includes a protruding portion formed in at least part of a region opposite the floating portion and protruding beyond the trench toward the floating portion side, and a recessed portion formed in at least part of a region opposite the mesa portion and recessed to the outside wiring portion side farther than the protruding portion.