Embodiments of the invention include forming a first transistor having first nanosheets, first dipole gate dielectric material being formed around the first nanosheets. An aspect includes forming a second transistor comprising second nanosheets, second dipole gate dielectric material being formed around the second nanosheets, the first and second transistors being in a vertical stack, a first spacing between the first nanosheets being different from a second spacing between the second nanosheets. An aspect includes forming a workfunction metal stack having a first workfunction metal and a second workfunction metal, the first and second workfunction metals being formed between the first nanosheets, the first workfunction metal being formed to pinch off in the second spacing between the second nanosheets such that the second workfunction metal is absent in the second spacing between the second nanosheets.

An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.

A high voltage field effect transistor includes a thick silicon oxide gate dielectric and polysilicon gate electrode, while a low voltage field effect transistor includes a high dielectric constant metal oxide gate dielectric and a metallic gate electrode.

A semiconductor device includes channel members vertically stacked, a gate dielectric layer wrapping around each of the channel members, a first work function (WF) layer disposed over the gate dielectric layer and wrapping around each of the channel members, a first WF isolation layer disposed over the first WF layer, a second WF layer disposed over the first WF isolation layer, a second WF isolation layer disposed over the second WF layer, and a metal fill layer disposed over the second WF isolation layer. The first WF layer has a uniform thickness. The second WF isolation layer is a nitride-containing layer.

A method of forming a semiconductor device includes depositing a target metal layer in an opening. Depositing the target metal layer comprises performing a plurality of deposition cycles. An initial deposition cycle of the plurality of deposition cycles comprises: flowing a first precursor in the opening, flowing a second precursor in the opening after flowing the first precursor, and flowing a reactant in the opening. The first precursor attaches to upper surfaces in the opening, and the second precursor attaches to remaining surfaces in the opening. The first precursor does not react with the second precursor, and the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor.

Disclosed is a semiconductor device comprising a first channel region, a first dielectric structure on the first channel region, a first metal pattern spaced apart from the first dielectric structure, and a first dipole structure between the first metal pattern and the first dielectric structure. The first dipole structure includes a first dipole layer and a second dipole layer. The first dipole layer includes a first dipole element. The second dipole layer includes a second dipole element different from the first dipole element. A maximum oxidation number of the first dipole element is different from a maximum oxidation number of the second dipole element.

A method includes forming a p-type transistor. The method includes forming a gate dielectric on a semiconductor region, and depositing a p-type work-function layer on the gate dielectric. The p-type work-function layer includes a metal nitride, which includes a first metal and a second metal. An n-type work-function layer is deposited over the p-type work-function layer. A p-type source/drain region is formed aside of the semiconductor region.

A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.

According to one embodiment, a semiconductor device includes a substrate, a first transistor, a second transistor, a first insulating portion, and a second insulating portion. The first transistor includes a first diffusion region and a second diffusion region, a first gate insulating film, and a first gate electrode. The second transistor includes a third diffusion region and a fourth diffusion region, a second gate insulating film, and a second gate electrode. The first insulating portion is positioned between the first gate electrode and the second gate electrode. The second insulating portion covers the first transistor, the second transistor, and the first insulating portion from a side opposite to the substrate. The first insulating portion and the second insulating portion are formed of different materials.

A semiconductor device may include a semiconductor substrate including first and second regions, a first gate structure on the first region, and a second gate structure on the second region. Each of the first and second gate structures may include a metal pattern, a high-k dielectric pattern between the semiconductor substrate and the metal pattern, and a work-function layer between the high-k dielectric pattern and the metal pattern. The work-function layer of the first gate structure may include a first metal element in the metal pattern of the first gate structure and a dipole material in the high-k dielectric pattern of the first gate structure, and the work-function layer and the high-k dielectric pattern in the second gate structure may include a metal oxide material. In the second gate structure, an oxygen content in the work-function layer may be higher than that in the high-k dielectric pattern.