Embodiments of the invention include forming a first transistor having first nanosheets, first dipole gate dielectric material being formed around the first nanosheets. An aspect includes forming a second transistor comprising second nanosheets, second dipole gate dielectric material being formed around the second nanosheets, the first and second transistors being in a vertical stack, a first spacing between the first nanosheets being different from a second spacing between the second nanosheets. An aspect includes forming a workfunction metal stack having a first workfunction metal and a second workfunction metal, the first and second workfunction metals being formed between the first nanosheets, the first workfunction metal being formed to pinch off in the second spacing between the second nanosheets such that the second workfunction metal is absent in the second spacing between the second nanosheets.

A semiconductor device includes a substrate, a first oxide layer and a second oxide layer. The substrate has a first region and a second region. The first oxide layer is disposed on the first region. The first oxide layer includes a first thermal oxide layer and a first deposited oxide layer, and a portion of the first thermal oxide layer is formed by a pad oxide layer. The second oxide layer is disposed on the second region. The second oxide layer includes a second thermal oxide layer and a second deposited oxide layer.

A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns spaced apart from the first lower pattern in a first direction, a first gate structure including first inner gates between the first lower pattern and a lowermost first sheet pattern of the first sheet patterns, and between each pair of adjacent first sheet patterns, the first inner gates extending in a second direction that intersects the first direction, where each of the first inner gates includes a first gate electrode and a first gate insulating film, first source/drain patterns on the first lower pattern and connected to the first sheet patterns, first inner spacers between the first source/drain patterns and the first inner gates, and first nitrogen build-up areas within the first inner spacers.

A semiconductor device includes a substrate having an I/O region and a core region; a first transistor in the I/O region; and a second transistor in the core region, wherein the first transistor includes a first gate structure having: an interfacial layer; a first high-k region over the interfacial layer; and a conductive layer over the first high-k region, wherein the second transistor includes a second gate structure having: the interfacial layer; a second high-k region over the interfacial layer; and the conductive layer over the second high-k region, and where in the first high-k region is thicker than the second high-k region.

Semiconductor devices and methods of manufacturing are presented wherein a gate dielectric is treated within an analog region of a semiconductor substrate. The gate dielectric may be treated with a plasma exposure and/or an annealing process in order to form a recovered region of the gate dielectric. A separate gate dielectric is formed within a logic region of the semiconductor substrate, and a first gate electrode and second gate electrode are formed over the gate dielectrics.

A high voltage field effect transistor includes a thick silicon oxide gate dielectric and polysilicon gate electrode, while a low voltage field effect transistor includes a high dielectric constant metal oxide gate dielectric and a metallic gate electrode.

A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, and a second transistor in the second region. The first transistor includes a first gate structure having an interfacial layer, a first high-k region over the interfacial layer, and a conductive layer over the first high-k region. The second transistor includes a second gate structure having the interfacial layer, a second high-k region over the interfacial layer, and the conductive layer over the second high-k region. The first high-k region is thicker than the second high-k region. The first transistor includes a first channel under the first gate structure. The first channel has first and second semiconductor materials alternately stacked. The first transistor includes a first source/drain (S/D) feature interfacing with both the first and second semiconductor materials in the first channel of the first transistor.

Disclosed is a semiconductor device comprising a first channel region, a first dielectric structure on the first channel region, a first metal pattern spaced apart from the first dielectric structure, and a first dipole structure between the first metal pattern and the first dielectric structure. The first dipole structure includes a first dipole layer and a second dipole layer. The first dipole layer includes a first dipole element. The second dipole layer includes a second dipole element different from the first dipole element. A maximum oxidation number of the first dipole element is different from a maximum oxidation number of the second dipole element.

A semiconductor device may include a semiconductor substrate including first and second regions, a first gate structure on the first region, and a second gate structure on the second region. Each of the first and second gate structures may include a metal pattern, a high-k dielectric pattern between the semiconductor substrate and the metal pattern, and a work-function layer between the high-k dielectric pattern and the metal pattern. The work-function layer of the first gate structure may include a first metal element in the metal pattern of the first gate structure and a dipole material in the high-k dielectric pattern of the first gate structure, and the work-function layer and the high-k dielectric pattern in the second gate structure may include a metal oxide material. In the second gate structure, an oxygen content in the work-function layer may be higher than that in the high-k dielectric pattern.

A semiconductor device includes a substrate, a metal gate and a poly gate. The substrate includes a first region and a second region. The metal gate is disposed on the first region of the substrate. The poly gate is disposed on the second region of the substrate. A gate area of the poly gate is greater than that of the metal gate.