A fin-shaped structure formed on a base substrate that could comprise a stack of alternating sacrificial layers and semiconductor layers. The stack materials could be removed relative to the dummy gates and relative to a mask formed before or after the dummy gates, creating lateral recesses with U-shaped sidewalls formed of stacked U-shaped portions of the sacrificial and semiconductor layers. Semiconductor material could be grown in the recesses by epitaxial growth, starting from the U-shaped semiconductor portions. The grown material could be lattice mismatched relative to the material of the U-shaped portions. No dislocations could be created due to oppositely interfering growth fronts, and a desired stress can thereby be created in at least one or more channel sheets of the eventual transistors. These transistors can be arranged in a forksheet configuration, after producing a trench to remove the mask, and filling the trench by a dielectric material.

Semiconductor structure and method of forming semiconductor structure are provided. The semiconductor structure includes a substrate, a first isolation structure, and a first nanostructure and a second nanostructure on two sides of the first isolation structure. The semiconductor structure also includes a second isolation structure, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure. A top of the second isolation structure is lower than a top of the first isolation structure. The semiconductor structure also includes a first gate structure and a second gate structure. The first gate structure and the second gate structure expose a top surface of the first isolation structure. The semiconductor structure also includes a third gate structure and a fourth gate structure. The third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.

An integrated circuit device includes a fin-type active region extending in a first horizontal direction on a substrate, a nanosheet stack including a plurality of nanosheets on the fin-type active region, a gate line extending around each of the plurality of nanosheets on the fin-type active region and extending in a second horizontal direction intersecting with the first horizontal direction, and a vertical structure at least partially overlapping the gate line in the second horizontal direction and including a side wall in contact with each of the plurality of nanosheets. The vertical structure further includes a recessed portion on the side wall thereof.

Techniques to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction between corresponding source or drain regions. The first and second semiconductor regions may include any number of nanosheets with first and second gate structures extending around three sides of each of the first and second semiconductor regions, respectively. A dielectric spine extends in the first direction directly between the first and second semiconductor regions. In an example, the gate dielectric of each of the first and second gate structures is still present between the first and second semiconductor regions and the dielectric spine. An uppermost width of the dielectric spine may be smaller (e.g., 5 nm or more smaller) than a lower width of the dielectric spine that is between the first and second gate structures.

An IC device comprising: a substrate comprising fin-type active areas spaced apart from each other with a separation recess therebetween in a first direction and protruding in a second direction; a sheet separation wall comprising a lower sheet separation wall and an upper sheet separation wall thereon, the sheet separation wall extending in a third direction along the separation recess; a sheet barrier pattern on a lower surface and/or at least a portion of a side surface of the upper sheet separation wall; nanosheet stacked structures on the fin-type active areas and spaced apart from each other in the first direction with the sheet separation wall therebetween, each of the nanosheet stacked structures comprising nanosheets; a gate electrode on the fin-type active areas and the nanosheet stacked structures; indent spacers between the nanosheets and the sheet separation wall; and spacer layers between the gate electrode and the sheet separation wall.

Various embodiments of the disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a first dielectric wall disposed over a substrate, and a first metal gate structure portion and a second metal gate structure portion disposed on opposing sides of the first dielectric wall, each comprising a plurality of semiconductor layers vertically stacked and separated from each other; a high-k dielectric layer surrounding at least three surfaces of each semiconductor layer, a gate electrode layer disposed between adjacent semiconductor layers, and a second dielectric wall disposed adjacent to the first metal gate structure portion, the second dielectric wall having a top surface at an elevation lower than a top surface of the first dielectric wall, and a metal layer disposed over the second dielectric wall and in contact with the gate electrode layer of the first and second metal gate structure portions.

An integrated circuit includes a transistor including a plurality of stacked channels. A first dielectric wall structure is positioned on a first lateral side of the stacked channels. A second dielectric wall structure is positioned on a second lateral side of the stacked channels. A dielectric home structure is positioned above the top channel. A gate electrode includes a vertical column extending vertically between the second dielectric wall structure and the stacked channels. The gate electrode includes finger portions extending laterally from the vertical column between the stacked channels.

A semiconductor device includes a semiconductor substrate, a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a dielectric wall, and a first isolation feature. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure are disposed on the semiconductor substrate. The first semiconductor structure is disposed between the second semiconductor structure and the third semiconductor structure. The dielectric wall is disposed on the semiconductor substrate and is connected between the first semiconductor structure and the second semiconductor structure. The first isolation feature is disposed between the first semiconductor structure and the third semiconductor structure, and extends into the semiconductor substrate.

The semiconductor device including a circuit region and a first-first overlay structure may be provided. The circuit region includes a lower separation pattern, an upper separation pattern, and a first gate electrode. The first-first overlay structure includes a first-first dummy gate group including first-first dummy gate patterns extending in a first direction, respectively, and arranged in a second direction, and a first-first dummy upper separation group including first-first dummy upper separation patterns being alternate with the first-first dummy gate patterns and between the first-first dummy gate patterns. At least a portion of one of the first-first dummy gate patterns is at the same level as at least a portion of the first gate electrode, and at least a portion of one of the first-first dummy upper separation patterns is at the same level as at least a portion of the upper separation pattern.

A semiconductor device includes an active pattern extending on a substrate in a first direction, channel patterns vertically stacked on the active pattern, a separation structure extending in a second direction and separating each of the active pattern and the channel patterns into first and second portions, a gate structure extending in the second direction and onto the first portions of the channel patterns, a separation pattern extending in the first direction, separating the first portions of the channel patterns into first and second channel patterns, and separating the gate structure into first and second gate structures, and a third gate structure extending in the second direction and onto the second portions of the channel patterns. The second portions of the channel patterns have a width greater than a sum of first and second widths of the first and second channel patterns, respectively.