Semiconductor devices and fabrication methods are provided. In one example, a semiconductor device includes: a substrate, a fin formed on the substrate, a gate structure formed on the fin, a metal contact formed on the fin and adjacent to the gate structure. The fin extends along a first horizontal direction, the gate structure and the metal contact extend along a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction. The gate structure further includes a gate electrode coupled to the fin and a dielectric gate isolation section separated from the gate electrode. The dielectric gate isolation section includes a dielectric material. A portion of the dielectric gate isolation section is aligned with a portion of the metal contact adjacent and proximate to the dielectric gate isolation section in the first horizontal direction.

A high voltage transistor may include a plurality of source/drain regions, a gate structure, and a gate oxide layer that enables the gate structure to selectively control a channel region between the source/drain regions. The gate oxide layer may extend laterally outward toward one or more of the plurality of source/drain regions such that at least a portion of the gate oxide layer is not under the gate structure. The gate oxide layer extending laterally outward from under the gate structure enables the gate oxide layer to be used as a self-aligned structure for forming the source/drain regions of the high voltage transistor. In particular, the gate oxide layer extending laterally outward from under the gate structure enables the gate oxide layer to be used to form the source/drain regions at a greater spacing from the gate structure without the use of additional implant masks when forming the source/drain regions.

Devices, transistor structures, systems, and techniques are described herein related to providing a backside passivation layer on a transistor semiconductor material. The semiconductor material is between source and drain structures, and a gate structure is adjacent a channel region of the semiconductor material. The passivation layer is formed as a conformal insulative layer on a backside of the semiconductor material and is then treated using an ozone/UV cure to remove trap charges from the semiconductor material.

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a first and a second fin-shaped active region over a substrate, the first and second fin-shaped active regions extending lengthwise along a first direction, forming a gate structure over channel regions of the first and second fin-shaped active regions, the gate structure extending lengthwise along a second direction substantially perpendicular to the first direction, forming a trench to separate the gate structure into two segments, the trench extending lengthwise along the first direction and being disposed between the first and second fin-shaped active regions, performing an etching process to enlarge an upper portion of the trench, and forming a gate isolation structure in the trench, and, in a cross-sectional view cut through both the first and second fin-shaped active regions and the gate structure, the gate isolation structure is a T-shape structure.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO.sub.2.

A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.

A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.

A method includes providing a semiconductor structure having a metal gate structure (MG), gate spacers disposed on sidewalls of the MG, and a source/drain (S/D) feature disposed adjacent to the gate spacers; forming a first metal layer over the S/D feature and between the gate spacers; recessing the first metal layer to form a trench; forming a dielectric layer on sidewalls of the trench; forming a second metal layer over the first metal layer in the trench, wherein sidewalls of the second metal layer are defined by the dielectric layer; and forming a contact feature over the MG to contact the MG.