The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate (101) and a first electrode (102) configured as either a source or a drain of the transistor. The device includes a second electrode (104) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer (103) that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion (107) and a gate insulating layer (106), which is arranged between the active layer (103) and a gate conductor portion (107) so as to prevent direct contact between the active layer (103) and the gate conductor portion (107). The active layer (103) comprises a 1D material arranged with its longitudinal axis parallel to the substrate (101) and/or a 2D material arranged with its plane substantially parallel to the substrate (101) The present disclosure further comprises a method (3000) for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.

The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate (101) and a first electrode (102) configured as either a source or a drain of the transistor. The device includes a second electrode (104) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer (103) that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion (107) and a gate insulating layer (106), which is arranged between the active layer (103) and a gate conductor portion (107) so as to prevent direct contact between the active layer (103) and the gate conductor portion (107). The active layer (103) comprises a 1D material arranged with its longitudinal axis parallel to the substrate (101) and/or a 2D material arranged with its plane substantially parallel to the substrate (101) The present disclosure further comprises a method (3000) for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.

A semiconductor device includes a semiconductor substrate having an active region in which a main switching element structure is formed, a current sense region in which a sense switching element structure is formed, and a peripheral region located around the active region and the current sense region. The semiconductor substrate is a 4H-SiC substrate having an off angle in a <11-20> direction. The current sense region is disposed in a range where the active region is not present when viewed along the <1-100> direction.

The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate and a first electrode configured as either a source or a drain of the transistor. The device includes a second electrode) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion and a gate insulating layer, which is arranged between the active layer and a gate conductor portion as to prevent direct contact between the active layer and the gate conductor portion. The active layer comprises a 1D material arranged with its longitudinal axis parallel to the substrate and/or a 2D material arranged with its plane substantially parallel to the substrate. The present disclosure further comprises a method for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.

A semiconductor device has a shape of a rectangular in which the side length in a first direction is greater than or equal to the side length in a second direction in a plan view, and includes 2n+1 obround first source pads of a first vertical MOS transistor that are arranged in stripes at positions within a first area and extend in the second direction and 2n+1 obround second source pads of a second vertical MOS transistor that are arranged in stripes at positions within a second area and extend in the second direction.

A semiconductor device has a shape of a rectangular in which the side length in a first direction is greater than or equal to the side length in a second direction in a plan view, and includes 2n+1 obround first source pads of a first vertical MOS transistor that are arranged in stripes at positions within a first area and extend in the second direction and 2n+1 obround second source pads of a second vertical MOS transistor that are arranged in stripes at positions within a second area and extend in the second direction.

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes: a substrate, a dielectric layer, a first gate structure and a second gate structure. The substrate includes discrete semiconductors arranged at a top of the substrate and extending in a vertical direction. The first gate structure is arranged in a first region of the semiconductor pillar and surrounds the semiconductor pillar. The second gate structure is arranged in a second region of the semiconductor pillar and includes a ring structure and at least one bridge structure. The ring structure surrounds the semiconductor pillar, and the at least one bridge structure penetrates through the semiconductor pillar and extends to an inner wall of the ring structure in a penetrating direction. The dielectric layer is located between the first gate structure and the semiconductor pillar, and between the second gate structure and the semiconductor pillar.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors each of which includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors and overlaying the second metal layer, each of first memory cells include at least one second transistor; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors and overlaying the third level, each of second memory cells include at least one fourth transistor, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one of the second transistors includes a hafnium oxide gate dielectric.

A vertically upright CMOS inverter includes a base substrate, a p-type semiconductor layer, an n-type semiconductor layer, and a first gate electrode. The p-type semiconductor layer includes a first hole doping area, a second hole doping area, and a first channel area. The n-type semiconductor layer includes a first electron doping area, a second electron doping area, and a second channel area.

A semiconductor device includes: a semiconductor layer that includes a semiconductor substrate on a back face side and is divided into a first region, a second region, and a third region that do not overlap each other and are not dispersedly disposed in a plan view of the semiconductor device; a first vertical metal-oxide-semiconductor (MOS) transistor provided in the first region of the semiconductor layer; a second vertical MOS transistor provided in the second region of the semiconductor layer; and a drain pad connected to the semiconductor substrate, at a position within the third region in the plan view of the semiconductor device. In the plan view of the semiconductor device, the third region is interposed between the first region and the second region. In the plan view of the semiconductor device, an area of the first region is larger than an area of the second region.