A method for manufacturing a semiconductor structure includes: forming an interconnect level structure having a first device region, a first side region aside the first device region, a second device region and a second side region aside the second device region; forming a dielectric layer over the interconnect structure, the dielectric layer including a first dielectric portion, a second dielectric portion, a first patterned portion and a second patterned portion that are respectively formed over the first device region, the second device region, the first side region, and the second side region, the first patterned portion and the second patterned portion being formed with different patterns; performing a planarization process on the dielectric layer; forming first recesses and second recesses respectively in the planarized first dielectric portion and the planarized second dielectric portion; and forming contact portion respectively in the first recesses and the second recesses.

A semiconductor structure includes a first stacked device having a first field-effect transistor containing one or more first nanosheet layers, a second field-effect transistor containing one or more second nanosheet layers; and a first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor, the first dielectric insulator layer having a first width. The semiconductor structure further includes a second stacked device adjacent the first stacked device. The second stacked device having a third field-effect transistor containing one or more third nanosheet layers, a fourth field-effect transistor containing one or more fourth nanosheet layers, and a second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor. The second dielectric insulator layer has a second width less than the first width of the first dielectric insulator layer.

A transistor device and method of fabrication are provided, where the transistor device may include a semiconductor substrate, a first dielectric layer disposed on a surface of the semiconductor substrate, a second dielectric layer disposed directly on the first dielectric layer, a gate structure disposed directly on the surface of the semiconductor substrate, and a spacer structure. A first opening through the first dielectric layer and the second dielectric layer may correspond to a gate channel. Portions of the first dielectric layer and the second dielectric layer may be interposed directly between portions of the gate structure and the surface of the semiconductor substrate. The spacer structure may be disposed in the gate channel and interposed between the gate structure and the semiconductor substrate. The spacer structure may contact respective side surfaces of the first dielectric layer and the second dielectric layer that at least partially define the gate channel.

An exemplary structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The body includes a first portion that is embedded in the plurality of first dielectric layers. The first portion comprises a first layer of first metal. The body further includes a second portion that is embedded in the plurality of second dielectric layers. The second portion comprises a first layer of second metal. A plurality of vias interconnect the first portion to the second portion through the active device layer. The first layer of the first portion mechanically connects the plurality of vias and the first layer of the second portion mechanically connects the plurality of vias.

A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

A semiconductor device includes a substrate, a first unit FET including first source, first drain, and first gate electrodes, a second unit FET including second source, second drain, and second gate electrodes, a first source wiring electrically contacting the first source electrode, a gate bus bar electrically connected to the first gate electrode, and interposing the first gate electrode between the gate bus bar and the second gate electrode, and a gate wiring provided above the first source electrode in non-contact with the first source electrode, and electrically connecting the gate bus bar and the second gate electrode, wherein a maximum width in a first direction of a region where the first source wiring contacts the first source electrode is times or more a maximum width in the first direction of a region where the first source wiring overlaps the first source electrode.

A transistor and a manufacturing method. The transistor includes a semiconductor base substrate, an active structure, a dielectric structure, and a gate stack structure. The active structure is formed on the semiconductor base substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region. The channel region includes at least two nanostructures stacked in a thickness direction of the semiconductor base substrate. In the channel region, a bottom nanostructure has a greater width than other nanostructures. The dielectric structure is formed between the semiconductor base substrate and the active structure. The dielectric structure is in contact with the bottom nanostructure. The gate stack structure is formed on a surface of the bottom nanostructure not in contact with the dielectric structure, and the gate stack surrounds a periphery of the other nanostructures.

A semiconductor device includes a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode, a second transistor unit having a second source electrode, a second gate electrode electrically, and a second drain electrode, a gate wiring provided on the substrate between the first source electrode and the second source electrode and electrically connected to the first gate electrode and the second gate electrode, a first cover metal layer provided above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, and electrically connected to the first source electrode, and a second cover metal layer provided above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring, and electrically connected to the second source electrode.

A semiconductor device includes a drain, a substrate, an epitaxial layer, and a semiconductor layer. The semiconductor layer includes a source region located on a side the semiconductor layer away from the epitaxial layer. A trench extending to the epitaxial layer is disposed on a side of the source region is away from the epitaxial layer. A gate, an electrode plate, a first shield gate, and a second shield gate are disposed in the trench. The electrode plate is located between the first shield gate and the second shield gate. The trench is further filled with an oxidized layer structure. The first shield gate and the second shield gate are separately spaced from the electrode plate to form electrode plate capacitance. One of the source region, the drain, and the gate is electrically connected to the electrode plate a first electrode, and a second one of the source region, the drain, and the gate is electrically connected to the shield gate structure.

Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.