An integrated circuit includes: a first device region and a second device region extending parallel to each other on a substrate in a first direction; a first gate electrode extending in a second direction and intersecting with the first device region and the second device region; a first transistor including the first gate electrode and a first channel having a first conductive-type in the first device region; and a second transistor including the first gate electrode and a second channel having the first conductive-type in the second device region, wherein a first source/drain region of the first transistor is electrically connected to a first source/drain region of the second transistor, and wherein a second source/drain region of the first transistor is electrically disconnected from a second source/drain region of the second transistor.

A semiconductor device includes: a substrate; a first active pattern including a first lower pattern and a first sheet pattern; a second active pattern spaced apart from the first active pattern in a first direction and including a second lower pattern and a second sheet pattern; a first gate electrode disposed on the first active pattern and elongated in the first direction; a second gate electrode disposed on the second active pattern and elongated in the first direction; a gate isolation insulating film disposed between the first and second gate electrodes and elongated in a second direction; and a blocking spacer disposed between the gate isolation insulating film and the first gate electrode, the blocking spacer disposed on a side surface of the first sheet pattern and the first lower pattern and elongated in a third direction perpendicular to an upper surface of the substrate.

A semiconductor device includes a substrate, a lower channel stack on the substrate, an upper channel stack on the lower channel stack, a gate electrode extending around the lower channel stack and the upper channel stack, a gate cut region that is on the substrate and includes an insulating material, a semiconductor material layer between the upper channel stack and the gate cut region, and an insulating layer that is between the semiconductor material layer and the upper channel stack.

Semiconductor devices according to some example embodiments include: a substrate; first channel patterns and second channel patterns that are spaced apart from each other on the substrate; an insulation structure between the first channel patterns and the second channel patterns; a gate structure that surrounds the first channel patterns, the second channel patterns, and at least a part of the insulation structure; and a source/drain pattern that is at both sides of each of the first channel patterns and the second channel patterns, wherein the insulation structure includes a first embedded insulation layer that is between the first channel patterns and the second channel patterns and extend in a first direction and a second embedded insulation layer between the first embedded insulation layer and the first channel patterns, and portions of the second embedded insulation layer are spaced apart from each other in the first direction.

A semiconductor device comprises a plurality of channel layers in a stacked configuration, and a gate structure disposed through respective ones of the plurality of channel layers. The gate structure is surrounded on at least three sides by portions of the respective ones of the plurality of channel layers. The gate structure is disposed from an uppermost channel layer of the plurality of channel layers to a lowermost channel layer of the plurality of channel layers.

A field effect transistor includes a substrate; an electron channel layer disposed on the substrate; a barrier layer disposed on the electron channel layer; a hole channel layer disposed on the barrier layer; a p-type doped semiconductor material layer disposed on the hole channel layer; a source electrode including a first portion in ohmic contact with the electron channel layer and a second portion in ohmic contact with the p-type doped semiconductor material layer; a drain electrode in ohmic contact with the electron channel layer; and a gate electrode disposed facing the p-type doped semiconductor material layer, between the source and drain electrodes.