A method of manufacturing a semiconductor device is provided, including: forming a first conductive type lightly doped region in the epitaxial layer; forming a first conductive type heavily doped region and a second conductive type heavily doped region in the epitaxial layer on the first conductive type lightly doped region, in which the neighboring first conductive type heavily doped regions are spaced apart by the second conductive type heavily doped region; disposing the mask on the second conductive type heavily doped region; disposing a spacer on a sidewall of the mask; doping a first conductive type dopant in the first conductive type lightly doped region to form an anti-breakdown region; removing the mask and forming a trench extending into the second conductive type heavily doped region, first conductive type lightly doped region and the epitaxial layer; and removing the spacer.

A semiconductor device is provided. The semiconductor device includes a substrate and channel structures stacked over each other along a first direction substantially perpendicular to a working surface of the substrate and each configured to have a current direction along a second direction substantially parallel to the working surface of the substrate. Source/drain (S/D) structures are positioned on opposing sides of the channel structure along the second direction. Gate structures are positioned on opposite sides of the channel structures along a third direction substantially parallel to the working surface of the substrate. The channel structures each have a shape of a nanosheet extending substantially perpendicular to the working surface of the substrate.

A multi-gate hybrid-channel field-effect transistor (FET) structure of an integrated device like a nanosheet device or a forksheet device comprises a substrate layer, a first layer stack and a second layer stack arranged side by side on the substrate layer, a first and second additional semiconductor channel layer arranged respectively besides the second layer stack, and a dielectric wall arranged on the substrate layer between the first layer stack and the second layer stack. The first and second layer stack each comprise one or more semiconductor channel layers and gate layers stacked alternatingly with respective surfaces parallel to the surface of the substrate layer. Respective surfaces of the first and second additional semiconductor channel layer are parallel to each other and perpendicular to the surface of the substrate layer.

Semiconductor structure and method of forming semiconductor structure are provided. The semiconductor structure includes a substrate, a first isolation structure, and a first nanostructure and a second nanostructure on two sides of the first isolation structure. The semiconductor structure also includes a second isolation structure, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure. A top of the second isolation structure is lower than a top of the first isolation structure. The semiconductor structure also includes a first gate structure and a second gate structure. The first gate structure and the second gate structure expose a top surface of the first isolation structure. The semiconductor structure also includes a third gate structure and a fourth gate structure. The third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.

An integrated circuit device includes a fin-type active region extending in a first horizontal direction on a substrate, a nanosheet stack including a plurality of nanosheets on the fin-type active region, a gate line extending around each of the plurality of nanosheets on the fin-type active region and extending in a second horizontal direction intersecting with the first horizontal direction, and a vertical structure at least partially overlapping the gate line in the second horizontal direction and including a side wall in contact with each of the plurality of nanosheets. The vertical structure further includes a recessed portion on the side wall thereof.

Provided is a semiconductor device which includes: a 1.sup.st transistor including a 1.sup.st channel structure extended in a 1.sup.st direction, and a 1.sup.st gate structure on the 1.sup.st channel structure; a 2nd transistor comprising a 2.sup.nd channel structure extended in the 1.sup.st direction, and a 2.sup.nd gate structure on the 2.sup.nd channel structure, the 2.sup.nd transistor being disposed adjacent to the 1.sup.st transistor in a 2.sup.nd direction that horizontally intersects the 1.sup.st direction; a 1.sup.st isolation wall between the 1.sup.st channel structure and the 2.sup.nd channel structure; and a 1.sup.st gate cut structure between the 1.sup.st gate structure and the 2.sup.nd gate structure on the 1.sup.st isolation wall in a 3.sup.rd direction that vertically intersects the 1.sup.st direction and the 2.sup.nd direction.

A microelectronic device includes a first source and drain structure adjacent to a second source and drain structure. A first conductive contact is in contact with a top surface and side surface of the first source and drain structure. A second conductive contact is in contact with a top surface and side surface of the second source and drain structure. The second conductive contact includes a via extension to connect to a backside component. A separating layer is located between the first conductive contact and the second conductive contact. A first sidewall of the separating layer is flush with the first conductive contact. A second sidewall of the separating layer is flush with the second conductive contact.

A semiconductor device includes a first active pattern and a second active pattern spaced apart from each other in a first direction, a first semiconductor pattern and a second semiconductor pattern overlapping the first active pattern, a third semiconductor pattern and a fourth semiconductor pattern overlapping the second active pattern, a lower isolation insulating layer between the first and second active patterns, source/drain patterns on the first and second active patterns and a gate electrode extending in the first direction. The first and third semiconductor patterns are arranged in the first direction as are the second and fourth semiconductor patterns. A width of the first semiconductor pattern in the first direction is greater than a width of the second semiconductor pattern in the first direction. A width of the third semiconductor pattern in the first direction is greater than a width of the fourth semiconductor pattern in the first direction.

Forksheet field-effect transistor (FET) devices are provided. A forksheet FET device includes a first FET having a first conductive gate material. The forksheet FET device includes a second FET that is adjacent the first FET and that has the first conductive gate material. Moreover, the forksheet FET device includes a conductive wall that separates the first FET from the second FET. The conductive wall includes a second conductive gate material that is different from the first conductive gate material.

Provided is a semiconductor device which includes: a 1.sup.st channel structure extended in a 1.sup.st direction; a 1.sup.st source/drain pattern on the 1.sup.st channel structure; a 2.sup.nd channel structure extended in the 1.sup.st direction at a side of the 1.sup.st channel structure in a 2.sup.nd direction intersecting the 1.sup.st direction; a 2.sup.nd source/drain pattern on the 2.sup.nd channel structure; and a 1.sup.st dielectric wall between the 1.sup.st channel structure and the 2.sup.nd channel structure, wherein the 1.sup.st source/drain pattern and the 2.sup.nd source/drain pattern are each of n-type, and a top surface and a side surface of each of the 1.sup.st channel structure and the 2.sup.nd channel structure is in a (110) orientation and in a (100) orientation, respectively.