A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

A method includes forming a first and a second gate dielectric on a first semiconductor channel region and a second semiconductor channel region overlapping the first semiconductor region, forming a first dipole film on the first gate dielectric, wherein the first dipole film comprises a first dipole dopant of a first type, and forming a second dipole film on the second gate dielectric. A drive-in process is performed to drive dipole dopants in the first dipole film and the second dipole film into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form a first transistor and a second transistor.

Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrating different materials into the channels for stacked transistor devices, for example in a CFET configuration, where the bottom device is an NMOS device and the top device is a PMOS device, or vice versa. Other embodiments may be described and/or claimed.

A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.

Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.

A material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into a transistor structure including a first stack of channel materials that is coupled to an n-type source and drain and in a vertical stack with a second stack of channel materials that is coupled to a p-type source drain. Within the first stack of channel material layers a first of two semiconductor material layers may be replaced with a first gate stack while within the second stack of channel materials a second of two semiconductor material layers may be replaced with a second gate stack.

A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.

A semiconductor structure includes a stacked device structure having a first field-effect transistor having a first source/drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor having a second source/drain region and a gate region having first sidewall spacers. The stacked device structure further includes a frontside source/drain contact disposed on a first portion of a sidewall and a top surface of the second source/drain region, a first metal via connected to the frontside source/drain contact and to a first backside power line, and second sidewall spacers disposed on a first portion of the first metal via. The first sidewall spacers comprise a first dielectric material and the second sidewall spacers comprise a second dielectric material different than the first dielectric material.

A method includes forming a lower transistor in a lower wafer, wherein the lower transistor includes a lower source/drain region, forming a contact plug electrically connecting to the lower source/drain region, and forming a metal line over the lower transistor. A first portion of the metal line is vertically aligned to the lower source/drain region. The method further includes bonding an upper wafer to the lower wafer, and forming an upper transistor in the upper wafer. The upper transistor includes an upper source/drain region, and is vertically aligned to a second portion of the metal line. A first interconnect structure is formed on the lower wafer and electrically connecting to the lower transistor. A second interconnect structure is formed on the upper wafer and electrically connecting to the upper transistor.