An IC includes first-third power rails over a semiconductor substrate. The first rail has a first polarity different from the second and third rails. The IC includes multiple first cells on the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each first cell includes a first height and a first structure having at least one transistor. For each first cell in the first row, the first structure is entirely between the first and second rails. Further, for each first cell in the second row, the first structure is between the first and third rails. The IC includes an extension cell arranged on the semiconductor substrate in the first row. The extension cell includes a second structure having at least one transistor. A portion of the second structure extends into the second row.

An IC is provided. The IC includes a first P-type FinFET and a second P-type FinFET. The first P-type FinFET includes a discontinuous SiGe fin. The second P-type FinFET includes a continuous Si-base fin. The IC further includes first source/drain regions on the discontinuous SiGe fin and second source/drain regions on the continuous Si-base fin. A first depth of the first source/drain regions is greater than a second depth of the second source/drain regions.

A semiconductor device includes a substrate including a first device region and a second device region, active regions spaced apart from each other on the substrate, having a constant width, extending in a first direction parallel to an upper surface of the substrate and including a first active region and a second active region provided on the first device region and a third active region and a fourth active region provided on the second device region, a plurality of channel layers provided on the active regions and configured to be spaced apart from each other in a direction perpendicular to the upper surface of the substrate, gate structures provided on the substrate and extending to cross the active regions and the plurality of channel layers, and source/drain regions provided on the active regions on at least one side of the gate structures.

An IC includes first-third power rails over a semiconductor substrate. The first rail has a first polarity different from the second and third rails. The IC includes multiple first cells on the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each first cell includes a first height and a first structure having at least one transistor. For each first cell in the first row, the first structure is entirely between the first and second rails. Further, for each first cell in the second row, the first structure is between the first and third rails. The IC includes an extension cell arranged on the semiconductor substrate in the first row. The extension cell includes a second structure having at least one transistor. A portion of the second structure extends into the second row.

A semiconductor device includes a substrate including a first device region and a second device region, active regions spaced apart from each other on the substrate, having a constant width, extending in a first direction parallel to an upper surface of the substrate and including a first active region and a second active region provided on the first device region and a third active region and a fourth active region provided on the second device region, a plurality of channel layers provided on the active regions and configured to be spaced apart from each other in a direction perpendicular to the upper surface of the substrate, gate structures provided on the substrate and extending to cross the active regions and the plurality of channel layers, and source/drain regions provided on the active regions on at least one side of the gate structures.