A semiconductor structure is provided. A logic cell with a logic function includes a plurality of first transistors in an active region over a semiconductor substrate, a second transistor in the active region, a third transistor in the active region, and first and second isolation structures on opposite edges of the active region and extending along the first direction. Each first transistor includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure.

A structure for extracting interconnect parasitic in a ring oscillator is disclosed. The ring oscillator comprises multiple logical units connected in head to tail series. The structure comprises parasitic resistance sub-structures and/or parasitic capacitance sub-structures each connected to a corresponding logical unit. The structure can be used to determine errors in extracting parasitic resistance of polysilicon interconnects and metal interconnects, and/or errors in extracting parasitic capacitance between the polysilicon interconnects and between the metal interconnects. Therefore, the parasitic extraction error can be calibrated accordingly to obtain more precise circuit simulation results and more accurate device model and BEOL model.

A semiconductor structure is provided. A logic cell with a logic function includes P-type and N-type transistors in first and second active regions over a semiconductor substrate, first and a second isolation structures on opposite edges of the first and second active regions, first and third transistors in the first and second active regions and between the first isolation structure and the P-type transistors, second and fourth transistors in the first and second active region and between the second isolation structure and the P-type transistors. Each of the N-type transistors and a respective P-type transistor shares a first gate electrode along the first direction. The first and third transistors share a second gate electrode extending along the first direction. The second and fourth transistors share a third gate electrode extending along the first direction. The P-type transistors and the N-type transistors are configured to perform the logic function.

A semiconductor device includes an oxide diffusion (OD) area; at least one first poly gate, formed above the OD area; and a plurality of second poly gates, formed on both sides of the at least one first poly gate and above the OD area. The plurality of second poly gates are OD edge dummy gates that are used to reduce length of oxide diffusion (LOD) effect, and at least a portion of the plurality of second poly gates are reused to implement at least one delay circuit.

A semiconductor device includes: a plurality of standard cells disposed on a frontside of a substrate, and respectively including at least one gate structure and at least one active region; a frontside buffer cell disposed on the frontside of the substrate and between at least some of the plurality of standard cells, and including at least one a Through-Silicon Via (TSV) penetrating through the substrate; and a backside buffer cell disposed on a backside of the substrate, which includes: a plurality of conductive layers disposed on the backside of the substrate; and a plurality of vias connecting the plurality of conductive layers; and an insulating layer surrounding the plurality of conductive layers and the plurality of vias, wherein each of the plurality of conductive layers includes signal conductive patterns electrically connected to the at least one TSV, and power conductive patterns electrically connected to a power source.