A semiconductor device may include a substrate including an active pattern, a device isolation layer defining the active pattern, a channel pattern on the active pattern, a gate electrode on the channel pattern, and a first isolation pattern and a second isolation pattern penetrating the gate electrode. The first isolation pattern may be extended into the device isolation layer, and the second isolation pattern may be provided to penetrate the gate electrode and the device isolation layer and may be extended into an upper portion of the substrate. A level of a bottom surface of the second isolation pattern may be lower than a level of a bottom surface of the device isolation layer.

A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.

An IC is provided. The IC includes a first P-type FinFET and a second P-type FinFET. The first P-type FinFET includes a discontinuous SiGe fin. The second P-type FinFET includes a continuous Si-base fin. The IC further includes first source/drain regions on the discontinuous SiGe fin and second source/drain regions on the continuous Si-base fin. A first depth of the first source/drain regions is greater than a second depth of the second source/drain regions.

In an aspect of the disclosure, apparatuses for reducing the cost of using an ECO standard cell library in chip design are provided. Such an apparatus may be a MOS device including several regions. The MOS device may include a pMOS transistor and an nMOS transistor in a first region of the device. The pMOS transistor gate of the pMOS transistor and the nMOS transistor gate of the nMOS transistor may be formed by a gate interconnect extending in a first direction across the device. The MOS device may include several unutilized pMOS transistors and several unutilized nMOS transistors in a second region of the device adjacent to the first region. Fins of the pMOS transistors and the nMOS transistors in the first region may be disconnected from fins of the unutilized pMOS transistors and the unutilized nMOS transistors in the second region.

A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.

A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

A semiconductor device is provided. The semiconductor device includes: first, second and third active patterns on a logic cell region of a substrate and are spaced apart from each other in a first direction; first and second gate electrodes, the first gate electrode crossing the first active pattern and the second gate electrode crossing the second active pattern; a first separation pattern provided between the first and second active patterns; a second separation pattern provided between the second and third active patterns; a first gate insulating layer interposed between the first gate electrode and the first active pattern; and a first gate cutting pattern interposed between the first and second gate electrodes, and in contact with a top surface of the first separation pattern. The first separation pattern is wider than the second separation pattern, and the first gate insulating layer extends between the first gate electrode and the first separation pattern, and contacts side and top surfaces of the first separation pattern.

The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.