Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.

According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.

An array switch circuit system includes a substrate, a plurality of first conductive pads, a plurality of first row/column switches, a plurality of second conductive pads and a plurality of first transmission lines. The first conductive pads are spaced apart from each other on the substrate and arranged as an array. Each of the first conductive pads has a column/row position in the array. Each of the first column/row switches connects two adjacent ones of the first conductive pad corresponding to the same column/row position. The plurality of second conductive pads are disposed on a periphery of the first conductive pad. Each of the first transmission lines connects two of the second conductive pads, and includes a first conductor strip and two second conducting strips. The two second conducting strips are respectively located on both sides of the first conducting strip and are coplanar with the first conducting strip.

A method includes fabricating a first-voltage underlayer power rail conductively connecting to the source region of a first-type transistor and fabricating a second-voltage underlayer power rail conductively connecting to the source region of a second-type transistor. Each of the first-voltage and second-voltage underlayer power rails extends in a first direction. The method also includes patterning a first connection layer to form a first-voltage power rail and a second-voltage power rail extending in the second direction which is perpendicular to the first direction. The first-voltage power rail is directly connected with the first-voltage underlayer power rail through a first via-connector and the second-voltage power rail is directly connected with the second-voltage underlayer power rail through a second via-connector.

An integrated circuit includes a first-voltage underlayer power rail and a second-voltage underlayer power rail extending in a first direction below a first connection layer. A first-type transistor and a second-type transistor are underneath the first connection layer. The source region of the first-type transistor is connected to the first-voltage underlayer power rail, and the source region of the second-type transistor is connected to the second-voltage underlayer power rail. The integrated circuit also includes a first-voltage power rail, a second-voltage power rail, and a signal conducting line, each of which extends in a second direction in the first connection layer. The first-voltage power rail is connected to the first-voltage underlayer power rail, and the second-voltage power rail is connected to the second-voltage underlayer power rail. The signal conducting line is conductively connected to either a terminal-conductor or a gate-conductor.

An embodiment semiconductor structure includes a first active region and a second active region extending along a first direction, a functional gate structure and a non-functional gate structure aligned with each other and extending along a second direction, and a metallization layer over the functional gate structure and the non-functional gate structure. The metallization layer defines a first metallization region, a second metallization region, and one or two middle metallization regions between the first metallization region and the second metallization region. The functional gate structure overlaps the first metallization region and overlaps one of the one or two middle metallization regions to define an overlapped portion of the one of the one or two middle metallization regions. The overlapped portion has a space defined therein sized for a connection feature between the functional gate structure and the one of the one or two middle metallization regions.

An arrayed switch circuitry includes contact units each of which includes a pad, a first row channel provided with a first switching element, a first column channel connected to the first row channel and provided with a second switching element, a connecting channel connecting the pad to the first row channel or the first column channel, a second row channel connected with the pad through a third switching element and a second column channel connected with the pad through a fourth switching element. The first row channels with the same row position are connected to each other, and the second row channels with the same row position are connected to each other. The first column channels with the same column position are connected to each other, and the second column channels with the same column position are connected to each other.