A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Gate structures formed from substantially rectangular shaped gate structure layout shapes positioned on a gate horizontal grid having at least seven gate gridlines within a region. A first-metal layer including first-metal structures formed from substantially rectangular shaped first-metal structure layout shapes is formed above top surfaces of the gate structures within the region. The first-metal structure layout shapes are positioned on a first-metal vertical grid having at least eight first-metal gridlines. At least six contact structures are formed from substantially rectangular shaped contact structure layout shapes in physical and electrical contact with corresponding ones of at least six of the gate structures. A total number of first-transistor-type-only gate structures equals a total number of second-transistor-type-only gate structures within the region. At least four transistors of a first transistor type and at least four transistors of a second transistor type collectively form part of a logic circuit within the region.

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

A first transistor has a gate electrode formed by a substantially linear portion of a first conductive structure. A second transistor has a gate electrode formed by a substantially linear portion of a second conductive structure. A third transistor has a gate electrode formed by a substantially linear portion of a third conductive structure. A fourth transistor has a gate electrode formed by a substantially linear portion of a fourth conductive structure. The substantially linear portions of the first, second, third, and fourth conductive structures extend in a first direction and are positioned in accordance with a gate pitch. Gate electrodes of the first and second transistors have a first size as measured in the first direction. Gate electrodes of the third and fourth transistors have a second size as measured in the first direction. The first size is at least two times the second size.

An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

A first conductive structure forms a gate electrode of a first transistor of a first transistor type. A second conductive structure forms gate electrodes of both a second transistor of the first transistor type and a first transistor of a second transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms gate electrodes of both a third transistor of the first transistor type and a third transistor of the second transistor type. Gate electrodes of the first and second transistors of the first transistor type are separated by a fixed pitch, as are the gate electrodes of the second and third transistors of the second transistor type. The gate electrodes of the first transistor of the first transistor type and the second transistor of the second transistor type are separated by at least the fixed pitch.

A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.