Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

A device includes first to third power/ground (PG) elements; a first set of at least three tracks between the first and second PG elements and a second set of at least three tracks between the second and third PG elements, the tracks being arranged in equal numbers between the first and second PG and second and third PG elements; a first row of cells overlapping the first set; and a second row of cells overlapping the second set. In the first row of cells, a first cell has a first height and a second cell has a greater height than the first height; in the second row of cells, a third cell has the first height and a fourth cell has a lesser height less than the first height; and a track configured as an in-cell PG track is aligned with a boundary of the second and fourth cells.

A semiconductor device may include a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the first source/drain patterns, the first channel pattern including first semiconductor patterns, which are spaced apart from each other in a stacked formation, a gate electrode on the first channel pattern, a first gate cutting pattern adjacent to the first channel pattern that penetrates the gate electrode, and a first spacer pattern between the first gate cutting pattern and the first channel pattern. The first spacer pattern may include a first remaining pattern adjacent to an outermost side surface of at least one of the first semiconductor patterns and a second remaining pattern on the first remaining pattern. The second remaining pattern may be spaced apart from the first gate cutting pattern.

A semiconductor structure includes a first transistor, a second transistor, a gate structure, and a first source/drain contact. The first transistor includes first nanostructures stacked from each other in a Z-direction, and a first source/drain feature and a second source/drain feature on opposite sides of the first nanostructures in an X-direction. The second transistor is arranged with the first transistor in a Y-direction. The second transistor includes second nanostructures stacked from each other in the Z-direction, and a third source/drain feature and a fourth source/drain feature on opposite sides of the second nanostructures in the X-direction. The gate structure extends in the Y-direction and wraps around the first nanostructures and the second nanostructures. The first source/drain contact extends in the Y-direction and is under and electrically connected to the second source/drain feature and the fourth source/drain feature.

A semiconductor device may include a substrate including a first active pattern and a second active pattern, which are spaced apart from each other in a first direction parallel to a top surface of the substrate, a device isolation layer between the first and second active patterns, a first source/drain pattern disposed on the first active pattern, a second source/drain pattern disposed on the second active pattern, a first active contact disposed on the first and second source/drain patterns, a barrier pattern interposed between the first active contact and the first source/drain pattern and between the first active contact and the second source/drain pattern and extended into a space between the first active contact and the device isolation layer, and an air gap interposed between the first active contact and the barrier pattern. The first active contact may be electrically connected to the first and second source/drain patterns.