A semiconductor device may include a substrate including an active pattern, a device isolation layer defining the active pattern, a channel pattern on the active pattern, a gate electrode on the channel pattern, and a first isolation pattern and a second isolation pattern penetrating the gate electrode. The first isolation pattern may be extended into the device isolation layer, and the second isolation pattern may be provided to penetrate the gate electrode and the device isolation layer and may be extended into an upper portion of the substrate. A level of a bottom surface of the second isolation pattern may be lower than a level of a bottom surface of the device isolation layer.

A semiconductor device includes: a plurality of cells including 1.sup.st cells arranged in a 1.sup.st row of a layout of the semiconductor device; and a 1.sup.st backside power rail and a 2.sup.nd backside power rail disposed below the 1.sup.st cells, extended in a 1.sup.st direction, and arranged in a 2.sup.nd direction intersecting the 1.sup.st direction, wherein the 1.sup.st backside power has a 1.sup.st width, and the 2.sup.nd backside power rail has a 2.sup.nd width which is different from the 1.sup.st width.

A semiconductor structure is provided. A logic cell with a logic function includes a plurality of first transistors in an active region over a semiconductor substrate, a second transistor in the active region, a third transistor in the active region, and first and second isolation structures on opposite edges of the active region and extending along the first direction. Each first transistor includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure.

An apparatus and method for efficiently creating layout of standard cells to improve floor planning of a chip. In various implementations, an integrated circuit uses multiple standard cells with an absence of diffusion breaks at cell boundaries. The standard cells use vertically stacked non-planer transistors. Multiple transistors are formed with an active region having a length between a source region and a drain region of a single transistor. Therefore, the active regions of these transistors are not formed across multiple gate terminals. By having active regions of these transistors formed across a single gate terminal of a single transistor, there is sufficient spacing to provide electrical isolation between two active regions of the two adjoining standard cells. This is true even when the two adjoining standard cells share a source/drain region at the cell boundaries. Accordingly, forming diffusion breaks at the edges of these standard cells can be skipped.

An IC includes first-third power rails over a semiconductor substrate. The first rail has a first polarity different from the second and third rails. The IC includes multiple first cells on the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each first cell includes a first height and a first structure having at least one transistor. For each first cell in the first row, the first structure is entirely between the first and second rails. Further, for each first cell in the second row, the first structure is between the first and third rails. The IC includes an extension cell arranged on the semiconductor substrate in the first row. The extension cell includes a second structure having at least one transistor. A portion of the second structure extends into the second row.

A semiconductor device includes a first power line extended in a first direction, a second power line extended in the first direction and spaced apart from the first power line in a second direction crossing the first direction, a filler cell electrically connected to the first and second power lines, and a first logic cell and a second logic cell spaced apart from each other in the first direction, with the filler cell interposed therebetween. The filler cell includes a first source/drain pattern and a second source/drain pattern, a first gate electrode between the first and second source/drain patterns, a third source/drain pattern and a fourth source/drain pattern, and a second gate electrode between the third and fourth source/drain patterns.

Integrated circuits including an integrated standard cell structure are provided. In an embodiment, an integrated circuit includes a first transistor gated by a first input and connected to a first power supply rail and an output, a second transistor gated by a second input and connected to the first power supply rail and the output, a floating third transistor and a fourth transistor that are connected to the first power supply rail and a third power supply rail, a fifth transistor gated by the first input and connected to a second power supply rail, a sixth transistor gated by the second input and connected to the second power supply rail, a seventh transistor gated by the second input and connected to the fifth transistor and the output, and an eighth transistor gated by the first input and connected to the sixth transistor and the output.

A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.

An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.