A method includes forming a first and a second gate dielectric on a first semiconductor channel region and a second semiconductor channel region overlapping the first semiconductor region, forming a first dipole film on the first gate dielectric, wherein the first dipole film comprises a first dipole dopant of a first type, and forming a second dipole film on the second gate dielectric. A drive-in process is performed to drive dipole dopants in the first dipole film and the second dipole film into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form a first transistor and a second transistor.

Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrating different materials into the channels for stacked transistor devices, for example in a CFET configuration, where the bottom device is an NMOS device and the top device is a PMOS device, or vice versa. Other embodiments may be described and/or claimed.

A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

A semiconductor device that has two transistors and a source/drain contact. The first transistor has a layer of semiconductor material that acts as a channel, a structure that serves as a gate and wraps around the semiconductor channel layer, and two epitaxy structures on either end of the semiconductor channel layer that function as the source and drain. The second transistor is situated above the first transistor and has similar components, including a semiconductor channel layer, gate structure, and source/drain epitaxy structures. The connection between the first and second source/drain epitaxy structures is made by a source/drain contact that passes through one of the second source/drain epitaxy structures. This contact is made up of a metal plug and a metal liner that lines the plug.

A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.

An integrated circuit device includes a first semiconductor layer, a second semiconductor layer, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a first contact plug. The second semiconductor layer is above the first semiconductor layer. The first and second semiconductor layers are vertically spaced apart from each other. The first source/drain epitaxial structure is on a side of the first semiconductor layer. The second source/drain epitaxial structure is on a side of the second semiconductor layer and above the first source/drain epitaxial structure. The first source/drain epitaxial structure has a portion extending beyond a sidewall of the second source/drain epitaxial structure from a top view. The first contact plug is over a frontside of the first source/drain epitaxial structure. The first contact plug overlaps the portion of the first source/drain epitaxial structure from the top view.

Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.

A material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into a transistor structure including a first stack of channel materials that is coupled to an n-type source and drain and in a vertical stack with a second stack of channel materials that is coupled to a p-type source drain. Within the first stack of channel material layers a first of two semiconductor material layers may be replaced with a first gate stack while within the second stack of channel materials a second of two semiconductor material layers may be replaced with a second gate stack.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors which each includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (PLL) circuit or at least one Digital-Lock-Loop (DLL) circuit.

A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.