A semiconductor device, a manufacturing method therefor, and an electronic apparatus that reduces a parasitic capacitance generated between an internal electrode and a board silicon to suppress waveform distortion and signal delay of high-frequency signals, thereby enabling a high-speed operation. A configuration to include: a board silicon; a silicon oxide film stacked on the board silicon; an inter-wiring-layer film having an internal electrode stacked on the silicon oxide film; a through-hole forming a stepped hole with a larger-diameter hole extending from the board silicon to the silicon oxide film and a smaller-diameter hole extending from the silicon oxide film to the internal electrode; an interlayer dielectric film stacked on a circumferential side surface of the larger-diameter hole and the board silicon; and a redistribution layer on an inner peripheral surface of the through-hole and the interlayer dielectric film and connected to the internal electrode.

An optical device and a method of fabricating the same are disclosed. The optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite to the first surface, first and second pixel structures, an inter-pixel isolation structure disposed in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. The second die layer includes a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.

A CMOS imaging sensor structure and a manufacturing method therefor. The CMOS imaging sensor structure comprises a pixel unit of the CMOS imaging sensor set on a semiconductor substrate, the pixel unit comprises a circuit device region and a first photosensitive region, the circuit device region is set on the frontside of the semiconductor substrate, the first photosensitive region is set correspondingly in the semiconductor substrate below the circuit device region, the circuit device region is isolated from the first photosensitive region by an isolation region, and the circuit device region is electrical connected with the first photosensitive region through a conductive trench, a fill factor of a photosensitive region is increased, and performances of a reading circuit is increased by a more optimized design scheme. A second photosensitive region of the pixel unit can also be set on the semiconductor substrate on a side of the circuit device region, thus a larger photosensitive region can be formed together with the first photosensitive region. The present invention also provides a manufacturing method for the CMOS imaging sensor structure.

To improve characteristics in a semiconductor apparatus manufactured from a wafer shared in a plurality of manufacturing processes. A semiconductor apparatus includes an opening for a pad, a wiring layer, and a dummy pattern. In the semiconductor apparatus, the opening for a pad is formed on a front surface of a substrate. In addition, in the semiconductor apparatus, a predetermined electrode pad is provided in the opening for a pad. In the semiconductor apparatus, a front surface-side wiring layer is formed in the substrate. In the semiconductor apparatus, a dummy pattern is formed around a dummy non-forming region penetrating up to the front surface-side wiring layer from a rear surface relative to the front surface.

A method for manufacturing one or more optical sensor packages includes forming a bonded wafer by bonding (i) a device wafer comprising a plurality of optical sensing pixels and (ii) a circuit wafer comprising application-specific-integrated-circuit configured to operate the optical sensing pixels, where the bonded wafer includes a device-wafer surface and a circuit-wafer surface. The method also includes forming a plurality of microlens arrays over the device-wafer surface, where each microlens of the microlens arrays corresponds to a particular optical sensing pixel. The method also includes forming a plurality of module-lens structures over the plurality of microlens arrays, where each module-lens structure corresponds to a particular microlens array of the plurality of microlens arrays. The method also includes forming electrical contacts over the circuit-wafer surface to establish electrical connections to the plurality of optical sensing pixels and the application-specific-integrated-circuit.

The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the etch stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.

A region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are formed separately in one oxide semiconductor film. The region containing a high proportion of crystal components is formed so as to serve as a channel formation region and the other region is formed so as to contain a high proportion of amorphous components. It is preferable that an oxide semiconductor film in which a region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are mixed in a self-aligned manner be formed. To separately form the regions which differ in crystallinity in the oxide semiconductor film, first, an oxide semiconductor film containing a high proportion of crystal components is formed and then process for performing amorphization on part of the oxide semiconductor film is conducted.

An image sensor, a level shifter circuit, and an operation method thereof are provided. The image sensor includes a pixel circuit and a pixel driving circuit. The pixel driving circuit includes first, second, third, fourth, fifth, and sixth transistors. A first terminal of the first transistor is coupled to a first voltage. A first terminal of the second transistor is coupled to the first voltage, and a control terminal of the second transistor is coupled to a control terminal of the first transistor and a second terminal of the first transistor. A first terminal of the third transistor is coupled to the second terminal of the first transistor, and a second terminal of the third transistor is coupled to a ground voltage. A first terminal of the fourth transistor is coupled to a second terminal of the second transistor and an output terminal.

An image sensor and an operating method thereof are provided. The image sensor includes a first pixel circuit, a first column readout circuit, and a second column readout circuit. The first pixel circuit includes a first pixel unit, a first transfer transistor, a first reset transistor, a first readout transistor, and a first capacitor. The first column readout circuit includes a first circuit node. The second column readout circuit includes a bias transistor. A first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to the first circuit node, and a second terminal of the first readout transistor is coupled to the bias transistor.