The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

A solid-state imaging device includes a second image sensor having an organic photoelectric conversion film transmitting a specific light, and a first image sensor which is stacked in layers on a same semiconductor substrate as that of the second image sensor and which receives the specific light having transmitted the second image sensor, in which a pixel for focus detection is provided in the second image sensor or the first image sensor. Therefore, an AF method can be realized independently of a pixel for imaging.

An image sensor pixel includes first, second and third PIN photodiodes having respective first, second and third widths, which are unequal to each other, and respective first, second and third absorption spectra associated therewith, which are unequal to each other. The first absorption spectra is a first linear combination of three color matching functions divided by a wavelength of light incident the image sensor, the second absorption spectra is a second linear combination of the three color matching functions divided by a wavelength of light incident the image sensor, and the third absorption spectra is a third linear combination of the three color matching functions divided by a wavelength of light incident the image sensor.

An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.

The present technology relates to a solid-state imaging device, a driving method therefor, and an electronic apparatus capable of acquiring a signal to detect phase difference and a signal to generate a high dynamic range image at the same time. The solid-state imaging device includes a pixel array unit in which a plurality of pixels that receives light of a same color is arranged under one on-chip lens. The plurality of pixels uses at least one pixel transistor in a sharing manner, some pixels out of the plurality of pixels are set to have a first exposure time, and other pixels are set to have a second exposure time shorter than the first exposure time. The present technology can be applied to, for example, a solid-state imaging device or the like.

Various examples are provided related to color and optical sensing with vertically stacked sensors. In one example, a vertical color sensing element includes a R-sensing channel layer including a first sensing material, G-sensing channel layer including a second sensing material, and a B-sensing channel layer including a third sensing material. First and second transparent insulating layer having first and second thicknesses are between the R and G sensing channel layers and the G and B sensing channel layers, respectively. The first and second thicknesses can be based upon focal lengths of R-light, G-light and B-light entering the vertical color sensing device. In another example, a vertical optical sensor can include a first sensing channel layer including a first sensing material, a transparent insulating layer, and a second sensing channel layer including a second sensing material. The first sensing material can be vdW-S and the second sensing material can be different.

A monolithic sensor for detecting infrared and visible light according to an example includes a semiconductor substrate and a semiconductor layer coupled to the semiconductor substrate. The semiconductor layer includes a device surface opposite the semiconductor substrate. A visible light photodiode is formed at the device surface. An infrared photodiode is also formed at the device surface and in proximity to the visible light photodiode. A textured region is coupled to the infrared photodiode and positioned to interact with electromagnetic radiation.

A bio-sensor includes a substrate having a light-sensing region thereon. A first dielectric layer, a diffusion barrier layer, and a second dielectric layer are disposed on the substrate. A trenched recess structure is formed in the second dielectric layer, which is filled with a light filter layer that is capped with a cap layer. A first passivation layer and a nanocavity construction layer are disposed on the cap layer. A nanocavity is formed in the nanocavity construction layer. The sidewall and bottom surface of the nanocavity is lined with a second passivation layer.

The present technique relates to a solid-state imaging device and an imaging apparatus that enable provision of a solid-state imaging device having superior color separation and high sensitivity.

The solid-state imaging device includes a semiconductor layer 11 in which a surface side becomes a circuit formation surface, photoelectric conversion units PD1 and PD2 of two layers or more that are stacked and formed in the semiconductor layer 11, and a longitudinal transistor Tr1 in which a gate electrode 21 is formed to be embedded in the semiconductor layer 11 from a surface 15 of the semiconductor layer 11. The photoelectric conversion unit PD1 of one layer in the photoelectric conversion units of the two layers or more is formed over a portion 21A of the gate electrode 21 of the longitudinal transistor Tr1 embedded in the semiconductor substrate 11 and is connected to a channel formed by the longitudinal transistor Tr1.

A solid-state imaging device includes a layout in which one sharing unit includes an array of photodiodes of 2 pixels by 4n pixels (where, n is a positive integer), respectively, in horizontal and vertical directions.