An optical blocking region formed with patterned metal reduces light reflection toward pixel sensors in a pixel sensor array. The optical blocking region may be formed of a metal nanoscale grid in order to reflect more light away from the pixel sensors. The optical blocking region may include a dielectric layer, supporting the patterned metal, with high absorption structures or shallow deep trench isolation structures in order to increase absorption and thus reduce light reflection toward the pixel sensors.

A solid-state imaging device includes a pixel including a photoelectric conversion element, a floating diffusion layer, a transfer transistor, a reset transistor, and an amplifier transistor, and a control unit configured to supply a first voltage to a gate of the reset transistor when the charges are accumulated in the photoelectric conversion element, the first voltage being set between a second voltage and a third voltage; subsequently supply the second voltage to the gate of the reset transistor when the reset transistor is turned on in order to reset the potential of the floating diffusion layer, and subsequently supply the third voltage to the gate of the reset transistor when the amplifier transistor outputs the signal based on the potential of the floating diffusion layer.

There is provided an imaging device that includes photovoltaic type pixels that have photoelectric conversion regions generating photovoltaic power for each pixel depending on irradiation light; and an element isolation region that is provided between the photoelectric conversion regions of adjacent pixels and in a state of substantially surrounding the photoelectric conversion region.

A solid-state image pickup device is provided which can inhibit degradation of image quality which may occur when a global electronic shutter operation is performed. A gate drive line for a first transistor of gate drive lines for pixel transistors is positioned in proximity to a converting unit.

An image sensor is described having a pixel cell unit. The pixel cell unit has first, second and third transfer gate transistor gates on a semiconductor surface respectively coupled between first, second and third visible light photodiode regions and a first capacitance region. The pixel cell unit has a fourth transfer gate transistor gate on the semiconductor surface coupled between a first infrared photodiode region and a second capacitance region.

A method for manufacturing a back-side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor with a vertical transfer gate structure for improved quantum efficiency (QE) and global shutter efficiency (GSE) is provided. A sacrificial dielectric layer is formed over a semiconductor region. A first etch is performed into the sacrificial dielectric layer to form an opening exposing a photodetector in the semiconductor region. A semiconductor column is formed in the opening. A floating diffusion region (FDR) is formed over the semiconductor column and the sacrificial dielectric layer. A second etch is performed into the sacrificial dielectric layer to remove the sacrificial dielectric layer, and to form a lateral recess between the FDR and the photodetector. A gate is formed filling the lateral recess and laterally spaced from the semiconductor column by a gate dielectric layer. The BSI CMOS image sensor resulting from the method is also provided.

Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.

Provided is a solid state imaging device including: a pixel portion where pixel sharing units are disposed in an array shape and where another one pixel transistor group excluding transfer transistors is shared by a plurality of photoelectric conversion portions; transfer wiring lines which are connected to the transfer gate electrodes of the transfer transistors of the pixel sharing unit and which are disposed to extend in a horizontal direction and to be in parallel in a vertical direction as seen from the top plane; and parallel wiring lines which are disposed to be adjacent to the necessary transfer wiring lines in the pixel sharing unit and which are disposed to be in parallel to the transfer wiring lines as seen from the top plane, wherein voltages which are used to suppress potential change of the transfer gate electrodes are supplied to the parallel wiring lines.

An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, and a charge overflow circuit. The charge storage region may be used to operate the image sensor array in global shutter mode. During high light level illumination, the charge overflow circuit may divert charge away from the photodiode such that only a predetermined portion of the accumulated charge remains in the photodiode. During low light level illumination all of the accumulated charge may be stored in the pixel photodiode. The charge overflow circuit may include a transistor and a resistor or capacitor. By implementing a charge overflow circuit, the size of the charge storage region may be reduced while still preserving the high dynamic range and low noise of the image sensor during all light illumination conditions.

A solid-state image pickup device is provided which can inhibit degradation of image quality which may occur when a global electronic shutter operation is performed. A gate drive line for a first transistor of gate drive lines for pixel transistors is positioned in proximity to a converting unit.