A potential of a charge retaining unit that retains a charge generated by photoelectric conversion is adjusted. An imaging element includes a photoelectric conversion unit, a charge retaining unit, a charge transfer unit, a reset unit, an image signal generating unit that generates an image signal, capacitive coupling wiring, and a potential adjustment unit. The photoelectric conversion unit is formed on a semiconductor substrate and performs photoelectric conversion of incident light. The charge retaining unit retains a charge generated by photoelectric conversion. The charge transfer unit transfers the charge generated by photoelectric conversion to the charge retaining unit. The reset unit discharges the charge retained in the charge retaining unit. The image signal generating unit generates an image signal on the basis of the charge retained in the charge retaining unit. The capacitive coupling wiring is different from wiring that transmits control signals of the charge transfer unit, the reset unit, and the image signal generating unit and wiring that transmits a generated image signal and is capacitively coupled to the charge retaining unit. The potential adjustment unit applies an adjustment signal for adjusting the potential of the charge retaining unit via the capacitive coupling wiring.

An optical device and a method of fabricating the same are disclosed. The optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite to the first surface, first and second pixel structures, an inter-pixel isolation structure disposed in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. The second die layer includes a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.

The present disclosure provides an image sensing computing unit and its operating method, an image sensing computer and an electronic device. Among them, the image sensing computing unit includes a first photosensitive unit and a second photosensitive unit. The second photosensitive unit is connected in series with the first photosensitive unit. The changing direction of the first threshold voltage of the first photosensitive unit when receiving light is opposite to the changing direction of the second threshold voltage of the second photosensitive unit when receiving light, so as to implement an in-situ logical operation between light input signals.

This application belongs to the technical field of semiconductor devices, and relates to a pixel circuit, a control method, and an image sensor, including: at least two pixel units arranged in an array, wherein transmission transistors of at least two pixels of at least one pixel unit are connected to a corresponding first group of transmission control lines, and a transmission transistor of one other pixel is connected to a corresponding second group of transmission control lines. Therefore, the pixel circuit, the control method and the image sensor provided in the present application can control the density of phase focus of the image sensor by controlling the first group of transmission control lines and the second group of transmission control lines without changing the structure of the pixel, the structure is simple, and the optical performance is good.

An image sensor includes a pixel array that includes a first pixel group located in a first row and including a first select transistor and a first floating diffusion region, a second pixel group located in a second row and including a second select transistor and a second floating diffusion region, and a column line connected to both the first pixel group and the second pixel group. While charges generated by a photoelectric conversion element of the first pixel group are transferred to the first floating diffusion region, the first select transistor is turned off, the second select transistor is turned on, and a first voltage is applied to the column line through the second select transistor. A photoelectric conversion element of the second pixel group generates charges prior to the photoelectric conversion element of the first pixel group, so as to be transferred to the second floating diffusion region.

Disclosed is an image sensor comprising a semiconductor substrate that includes first through fourth pixel regions, each including first through fourth photoelectric conversion sections, and a pixel separation structure disposed in the semiconductor substrate and separating the first through fourth pixel regions from each other. The second pixel region is spaced apart in a first direction from the first pixel region. The fourth pixel region is spaced apart in a second direction from the first pixel region. The second direction intersects the first direction. The semiconductor substrate includes first impurity sections disposed on corresponding central portions of the first through fourth pixel regions, and a second impurity section disposed between the second and fourth pixel regions. Impurities doped in the first impurity sections have a conductivity type different from that of impurities doped in the second impurity section.

The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

An image sensor includes a first photodiode group, a second photodiode group, a first transfer transistor group, a second transfer transistor group, a floating diffusion region of a substrate in which electric charges generated in the first photodiode group are stored, and a power supply node for applying a power supply voltage to the second photodiode group. A barrier voltage is applied to at least one transfer transistor of the second transfer transistor group. The power supply voltage allows electric charges, generated in the second photodiode group, to migrate to the power supply node, and the barrier voltage forms a potential barrier between the second photodiode group and the floating diffusion region.

An image sensor, a level shifter circuit, and an operation method thereof are provided. The image sensor includes a pixel circuit and a pixel driving circuit. The pixel driving circuit includes first, second, third, fourth, fifth, and sixth transistors. A first terminal of the first transistor is coupled to a first voltage. A first terminal of the second transistor is coupled to the first voltage, and a control terminal of the second transistor is coupled to a control terminal of the first transistor and a second terminal of the first transistor. A first terminal of the third transistor is coupled to the second terminal of the first transistor, and a second terminal of the third transistor is coupled to a ground voltage. A first terminal of the fourth transistor is coupled to a second terminal of the second transistor and an output terminal.

An image sensor and an operating method thereof are provided. The image sensor includes a first pixel circuit, a first column readout circuit, and a second column readout circuit. The first pixel circuit includes a first pixel unit, a first transfer transistor, a first reset transistor, a first readout transistor, and a first capacitor. The first column readout circuit includes a first circuit node. The second column readout circuit includes a bias transistor. A first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to the first circuit node, and a second terminal of the first readout transistor is coupled to the bias transistor.