Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

An image sensor includes: a first device isolation part in a substrate and defining an active region; a first gate electrode having a first and second gate sidewalls; and a first impurity region and a second impurity region adjacent to the first and second gate sidewalls, wherein the active region includes: a first active central part; a first active protrusion; and a second active protrusion, wherein the first device isolation part has a first isolation sidewall overlapping the first active central part, and wherein a first straight line is at least partially spaced apart from the first isolation sidewall, wherein the first straight line links a first point, at which the first active protrusion meets the first active central part, to a second point, at which the second active protrusion meets the first active central part.

There is provided a structure to improve BSI global shutter efficiency. In a sensor pixel circuit, at least one strong electric field is formed at the position of a floating diffusion region to accordingly have the effect of shielding the floating diffusion region. Or, the semiconductor material from the floating diffusion node toward a light incident direction is removed in the manufacturing process such that a depletion region cannot be formed in this direction. Or, a reflection layer or a photoresist layer is formed in the light incident direction to block the light. In these ways, charges generated by the undesired noises are reduced, and noise charges are difficult to reach the floating diffusion region thereby improving the shutter efficiency.

An imaging device in which noise can be reduced, and an electronic device using this device. The imaging device includes a light receiving element, and a read circuit. A field effect transistor in the read circuit has a semiconductor layer in which a channel is formed, a gate electrode that covers the semiconductor layer, and a gate insulating film disposed between the semiconductor layer and the gate electrode. The semiconductor layer has a main surface, and a first side surface on one end side of the main surface in a gate width direction of the field effect transistor. The gate electrode has a first portion that faces the main surface via the gate insulating film, and a second portion that faces the first side surface via the gate insulating film. A crystal plane of the first side surface is a plane or a plane equivalent to the plane.

An imaging device connected to a neural network is provided. An imaging device having a neuron in a neural network includes a plurality of first pixels, a first circuit, a second circuit, and a third circuit. Each of the plurality of first pixels includes a photoelectric conversion element. The plurality of first pixels is electrically connected to the first circuit. The first circuit is electrically connected to the second circuit. The second circuit is electrically connected to the third circuit. Each of the plurality of first pixels generates an input signal of the neuron. The first circuit, the second circuit, and the third circuit function as the neuron. The third circuit includes an interface connected to the neural network.

An electronic device including a substrate, a silicon transistor disposed on the substrate, an oxide transistor disposed on the substrate and electrically connected to the silicon transistor, and a sensor configured to receive a light and output a signal. The silicon transistor and the oxide transistor are operated corresponding to the signal.

The re is provided a fingerprint identification module, including a substrate having a fingerprint identification area and a peripheral area; a photoelectric sensing structure in the fingerprint identification area, and including pixel units; each pixel unit includes a thin film transistor having a gate electrode coupled to a corresponding gate line and a first electrode coupled to a corresponding signal sensing line; the fingerprint identification area includes a photosensitive region, the pixel unit in the photosensitive region further includes a photoelectric sensor including a third electrode, a photosensitive pattern and a fourth electrode which are sequentially stacked along a direction away from the substrate, and the third electrode is coupled to a second electrode of the thin film transistor in the same pixel unit as that where the photoelectric sensor is located; an area ratio of the photoelectric sensor to the pixel unit corresponding thereto ranges from 40% to 90%.

Various embodiments of the present disclosure are directed towards a method for forming a pixel sensor. The method comprises forming a photodetector in a substrate. The substrate is patterned to define an opening above the photodetector. A gate electrode is formed within the opening, where the gate electrode has a top conductive body overlying a bottom conductive body. A first segment of a sidewall of the top conductive body contacts the bottom conductive body. A floating diffusion node is formed in the substrate laterally adjacent to the gate electrode. A second segment of the sidewall of the top conductive body overlies the floating diffusion node.

Provided is a light detection device which allows influence on adjacent pixels to be reduced. The light detection device includes a first substrate portion, a second substrate portion, and a through via. The first substrate portion has a pixel configured to photoelectrically convert incident light. The second substrate portion has a readout circuit configured to output a pixel signal based on charge output from the pixel to a signal line. The through via configured to connect the first substrate portion and the second substrate portion. The pixel has a floating diffusion configured to temporarily retain charge generated by photoelectric conversion. The readout circuit has a first pixel transistor connected to the floating diffusion through the through via and a second pixel transistor connected to the first pixel transistor and the signal line. The through via is provided, in plan view, in a direction orthogonal to a wiring path configured to connect between a contact portion of the first pixel transistor and a contact portion of the second pixel transistor in a region of the pixel.

The present invention has an object of improving the operation stability of a semiconductor device that detects radiations without decreasing the yield thereof. A semiconductor device includes an active matrix substrate (50) including a plurality of TFTs (10) and a plurality of pixel electrode (20); a photoelectric conversion substrate (62) located to face the active matrix substrate (50); an upper electrode (64) provided on a surface of the photoelectric conversion substrate (62) opposite to the active matrix substrate (50); and a plurality of connection electrodes (72) provided between the active matrix substrate (50) and the photoelectric conversion substrate(62), the plurality of connection electrodes (72) being formed of metal material. Each of the plurality of connection electrodes (72) is in direct contact with any of the plurality of pixel electrodes (20) and with the photoelectric conversion substrate (62), overlaps a semiconductor layer (14) of any of the plurality of TFTs (10) as seen in a direction normal to the active matrix substrate (50), and contains a metal element having an atomic number of 42 or greater and 82 or smaller.