A photoelectric packaging structure, and a preparation method of the photoelectric packaging structure, and a camera module having the photoelectric packaging structure are provided. The photoelectric packaging structure includes a substrate module and a photosensitive chip. The substrate module includes a substrate, and the substrate module defines a plurality of channels. The photosensitive chip is located on the substrate, and includes a photosensitive area and a non-photosensitive area connected to the photosensitive area. Two ends of each of the channels extend to the substrate and the non-photosensitive area, respectively. A conductive layer is formed on an inner wall of each of the channels to form a hollow conductive channel. The hollow conductive channel is electrically connected to the substrate and the non-photosensitive area.

A semiconductor device, a manufacturing method therefor, and an electronic apparatus that reduces a parasitic capacitance generated between an internal electrode and a board silicon to suppress waveform distortion and signal delay of high-frequency signals, thereby enabling a high-speed operation. A configuration to include: a board silicon; a silicon oxide film stacked on the board silicon; an inter-wiring-layer film having an internal electrode stacked on the silicon oxide film; a through-hole forming a stepped hole with a larger-diameter hole extending from the board silicon to the silicon oxide film and a smaller-diameter hole extending from the silicon oxide film to the internal electrode; an interlayer dielectric film stacked on a circumferential side surface of the larger-diameter hole and the board silicon; and a redistribution layer on an inner peripheral surface of the through-hole and the interlayer dielectric film and connected to the internal electrode.

A voltage to be applied to a charge holding section to which charges generated by a plurality of photoelectric conversion sections are transferred is adjusted. An imaging element includes a plurality of photoelectric conversion sections, a charge holding section, a plurality of charge transfer sections, an image signal generation section, and a plurality of capacitive coupling wirings. The photoelectric conversion section performs photoelectric conversion of incident light to generate a charge. The charge holding section holds the generated charge. The charge transfer section is arranged for each photoelectric conversion section and transfers the generated charge to the charge holding section. The image signal generation section generates an image signal corresponding to the held electric charge. The capacitive coupling wirings are capacitively coupled to the charge holding section, and are individually applied with an adjustment signal for adjusting the potential of the charge holding section.

A potential of a charge retaining unit that retains a charge generated by photoelectric conversion is adjusted. An imaging element includes a photoelectric conversion unit, a charge retaining unit, a charge transfer unit, a reset unit, an image signal generating unit that generates an image signal, capacitive coupling wiring, and a potential adjustment unit. The photoelectric conversion unit is formed on a semiconductor substrate and performs photoelectric conversion of incident light. The charge retaining unit retains a charge generated by photoelectric conversion. The charge transfer unit transfers the charge generated by photoelectric conversion to the charge retaining unit. The reset unit discharges the charge retained in the charge retaining unit. The image signal generating unit generates an image signal on the basis of the charge retained in the charge retaining unit. The capacitive coupling wiring is different from wiring that transmits control signals of the charge transfer unit, the reset unit, and the image signal generating unit and wiring that transmits a generated image signal and is capacitively coupled to the charge retaining unit. The potential adjustment unit applies an adjustment signal for adjusting the potential of the charge retaining unit via the capacitive coupling wiring.

Circuitry is provided that includes a first die, a second die, and a third die that are vertically stacked. The second die may have a front side facing the third die and a back side facing the first die. The first die can include a plurality of single-photon avalanche diodes (SPADs). The second die can include a plurality of switches coupled to cathode terminals of the plurality of SPADs in the first die. The third die can include digital readout logic coupled to the plurality of switches in the second die. The plurality of switches in the second die can be power using a high voltage and are sometimes referred to as analog high voltage switches. The digital readout logic in the third die can be power using a voltage that is lower than the high voltage being used to power the second die.

An optical device and a method of fabricating the same are disclosed. The optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite to the first surface, first and second pixel structures, an inter-pixel isolation structure disposed in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. The second die layer includes a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.

A photoelectric conversion device includes first and second semiconductor components. A semiconductor layer of the first semiconductor component includes a pixel array unit. First and second elements are included in a semiconductor layer different from the first semiconductor layer. At a bonding surface, first and second insulating films are bonded, and first and second metal portions are bonded. A first pixel generating a signal corresponding to brightness and the first element are connected through the first metal portion. A second pixel generating an event signal and the second element are connected through a second metal portion. A first conductor included in a first electrical path and positioned in a predetermined layer between first and fourth surfaces is provided, and a second conductor included in a second electrical path and positioned in the predetermined layer is provided. The first and second conductors are different in size.

An image sensor is provided. The image sensor includes a semiconductor substrate including a first surface, and a second surface opposite to the first surface, the semiconductor substrate further including a photoelectric conversion region; a transmission gate disposed on the first surface of the semiconductor substrate; a buried insulation layer disposed on the first surface of the semiconductor substrate to cover the transmission gate; and a pixel isolation structure disposed in a pixel isolation trench, the pixel isolation trench extending toward the second surface of the semiconductor substrate from the first surface of the semiconductor substrate and passing through the buried insulation layer, the pixel isolation structure defining a plurality of pixels in the semiconductor substrate, a portion of the pixel isolation structure being covered by the buried insulation layer.

A dual vertical transfer gate, a transistor including the same, and a CMOS image sensing device including the same. In some embodiments, a gate of the dual vertical transfer transistor may include a pair of poles, which are extended to an n-type region of a photodiode, and a connecting portion, which connects the paired poles to each other. A first insulating pattern may be provided between the poles and on the substrate.

The present application discloses an optical semiconductor device. The optical semiconductor device includes a logic die including a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and including a memory cell area and a memory peripheral area, and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, and a second intra-die via positioned in the sensor peripheral area. A height of the first intra-die via is greater than a height of the second intra-die via.